Texas Instruments TMS320C3 Series, User Manual, Page: 47 / 166

DSK Communications Kernel
4-13 Functional Overview
Table 4–1. Single-Step Pipeline Flow
Cycle Description Fetch Decode Read Execute
1
BUD R5
2
or 2000h,ST BUD R5
3
ldi @_R5,
R5
or 2000h,ST BUD R5
4
ldp @_DP,DP ldi @_R5,R5 or 2000h,ST BUD R5
5 Set global interrupt enable
USER1 ldp @_DP,DP ldi @_R5,R5 or 2000h,ST
6 Interrupt recognized
USER2 USER1 ldp @_DP,DP ldi @_R5,R5
7 Jam interrupt in pipeline (dis-
card USER2 fetch) – – –
XINT1 USER1 ldp @_DP,DP
8 Execute USER1 instruction – – – – – –
XINT1 USER1
9 Clear interrupt flag; clear
GIE; store return address on
stack; read vector table – – – – – – – – –
XINT1
10 Pipeline begins to fill with in-
terrupt service routine
XSTEP ISR
– – – – – – – – –
11 Pipeline continues to fill with
ISR
ISR2 XSTEP ISR
– – – – – –
12 Pipeline continues to fill with
ISR
ISR3 ISR2 XSTEP ISR
– – –
13 Execute first instruction of
ISR
ISR4 ISR3 ISR2 XSTEP ISR
Table 4–1 describes the pipeline flow that sets the XINT1 interrupt and
branches to your code. This table shows that the activities in the pipeline are
coordinated so that the code is fetched at the same time global interrupts are
enabled. In this way, the interrupt is placed in the pipeline right after fetching
the second instruction. This instruction is discarded and the pipeline is filled
with the interrupt service routine (ISR).
Note:
Another way of interpreting CPU interrupts is to treat them as a special kind
of opcode that is inserted into the pipeline. Instructions that are in the pipeline
before the interrupt occurs must complete execution.