Texas Instruments TMS320C3 Series, User Manual, Page: 137 / 166

Communications Kernel Source Code
A-9 Communications Kernel Source Code
;====================================================================;
; The XCTXT command returns the address of the context save area to ;
; the host. Subsequently, the host can use this address to ’get’ ;
; and put the CPU registers to modify the exectution of the processor;
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
XCTXT ldi @CPUCTXT,R0 ; Transmit location of context to CPU
call W_HOST ;
; b SR2 ;
;====================================================================;
; SR2 is the short ’common’ return sequence used by most commands. ;
; when executed, the return will send the CPU back to the users code ;
;====================================================================;
SR2 ldi 07F00h,AR0 ; Dummy non–HPI read releases READY
ldi *AR0,AR0 ;
pop AR1 ; restore ISR variables
pop AR0 ;
pop IR1 ;
pop R0 ;
pop DP ;
; andn 0x4,IF ;
; or 4,IE ;
pop ST ;
reti ; return to original code
;====================================================================;
; TMS320C31 SECONDARY VECTOR TABLE ;
; –––––––––––––––––––––––––––––––– ;
; When the TMS320C31 receives an interrupt it first fetches an ;
; address from the primary vector table (located in the bootloader ;
; ROM). This 32 bit value is then used as an address where the ;
; new execution begins. ;
; ;
; Since it is impossible to relocate the vector table, or modify ;
; the contents of the bootloader ROM, a ’secondary’ or ’branch’ ;
; vector table is used to direct execution to the correct routines. ;
; In this case the C31’s primary vector table has been filled with ;
; interrupt routine addresses which point to the upper memory of ;
; internal RAM beginning at 0x809FC0. Since these locations are ;
; were execution actually begins, and can be modified, a branch ;
; opcode can be used to direct execution to the desired location. ;
;====================================================================;
.sect ”vectors”
INT0 b $ ; 0x809FC1 0x001
INT1 b $ ; 0x809FC2 0x002
INT2 b INTx ; 0x809FC3 0x004 <– HPI
INT3 b $ ; 0x809FC4 0x008
XINT0 b $ ; 0x809FC5 0x010
RINT0 b $ ; 0x809FC6 0x020
XINT1 b SSTEP ; 0x809FC7 0x040 <– SSTEP
RINT1 b SSTEP; TRAPFIX ; 0x809FC8 0x080 <– ETRAP 0x74000008
TINT0 b $ ; 0x809FC9 0x100
TINT1 b $ ; 0x809FCA 0x200
DINT b $ ; 0x809FCB 0x400