Texas Instruments TMS320C3 Series, User Manual, Page: 151 / 166

Host Interface Control Design Notes
B-11 DSK Circuit Board Dimensions and Schematic Diagrams
Host Interface Control Design Notes
TITLE HOST INTERFACE CONTROL
DWG. NAME TMS320C3X DSK
ASSY # D600335–0001
PAL # U7
COMPANY TEXAS INSTRUMENTS INCORPORATED
ENGR KEITH LARSON
DATE 3/7/96
;
; DESIGN NOTES:
;
; The power consumption of the TMS320C31 DSK was considerably lowered by
; the use of a CMOS TIBPAL22V10Z. When clocked at 25MHz (H1 rate) the
; TIBPAL22V10Z typicaly consumes 40mA (80mA max) as compared to 200mA for
; bipolar PAL devices. If lower consumption is needed the TMS320C31 can be
; programmed to use the LOPOWER or IDLE2 when full speed execution is not
; required. LOPOWER essentially runs the DSP at 1/16 of full speed and
; IDLE2 shuts the the clock completely off. This results in 1/16 and
; practically zero power for these modes respectively for both the PAL
; and the DSP. However due to the 25nS propogation delay through the
; TIBPAL22V10Z a wait state is required for host and peripheral decodes.
;
; Memory access times for the /SRAM decoded output are as follows
;
; TIBPAL22V10Z (CMOS) at 50MHz, H1 = 40ns:
;
; t–access = H1 * (1 + WS) – Tpal – ( Td(H1L–A) – Tsu(D)R )
; t–access = H1 * (1 + WS) – 25ns – 19ns
;
; wait states ==> 0 1 2 3 4 ...
; t–access read ==> –4 36 76 116 156 ...
;
; IDLE2 wakeup is initiated by asserting the INT2 pin low. Since the
; clock is stopped during IDLE2, gating with synchronized signals cannot
; be used. A buffer is used with INT2 to avoid differences in the logic
; thresholds of the PAL22V10 and the C31 and to improve the rise and fall
; time of that signal.
;
; TRI–COLOR LED (POWER AND PWM)
; –––––––––––––––––––––––––––––
; If a logic high is applied to PWM (default state), the outputs /UBOOT
; and /USERX become an XOR and /XOR of T0 and T1. The XOR gate in this
; case is being used to detect the phase angle between T0 and T1. Therefor
; if T0 and T1 are configured as outputs, such as when the debugger is
; started, the color can be controled by adjusting the timers.
;
;
; USING THE PWM AS A DAC:
; –––––––––––––––––––––––
; If the output is filtered to a DC level by a low pass filter the
; DC level can be controlled by setting the two timers to identical
; freqencies seperated by a constant phase angle (delay). Since both the
; XOR and /XOR are provided a differential signal is also available.
;