Texas Instruments TMS320C3 Series, User Manual, Page: 133 / 166

Communications Kernel Source Code
A-5 Communications Kernel Source Code
;========================================================================;
; SSTEP ;
; This section of code is executed after the pending interrupt, which ;
; was set in XSTEP, has feteched the ISR vector and begun execution. ;
; This code performs a full CPU context save before going to the spin ;
; loop to await further commands. ;
;========================================================================;
SSTEP push DP ; temp storage of user DP
ldp @_ST ; DP for kernal
sti ST,@_ST ; store ST
sti IR0,@_IR0 ; IR0 used as temp, later for indexed store
pop IR0 ; save user DP
sti IR0,@_DP ;
pop IR0 ; save user PC
sti IR0,@_PC ;
sti SP,@_SP ; save user SP
sti BK,@_BK ; Block size
sti IE,@_IE ; Internal int enable
sti IF,@_IF ; CPU interrupt flags
sti IOF,@_IOF ; IO flags
sti RS,@_RS ; Repeat start
sti RE,@_RE ; Repeat end
sti RC,@_RC ; Repeat counter
; sti IR0,@_IR0 ; Keep everything <– IR0 Saved previously
sti IR1,@_IR1 ;
;– – – – – – – – – – – –
sti AR0,@_AR0 ; Use parallel opcodes for squeeze
sti AR1,@_AR1 ;
ldi @CPUCTXT,AR0 ;
ldi AR0,AR1 ;
addi 1,AR1 ;
ldi 2,IR0 ;
;– – – – – – – – – – – –
stf R0,*AR0++(IR0) ; Store floats
|| stf R1,*AR1++(IR0) ;
stf R2,*AR0++(IR0) ;
|| stf R3,*AR1++(IR0) ;
stf R4,*AR0++(IR0) ;
|| stf R5,*AR1++(IR0) ;
stf R6,*AR0++(IR0) ;
|| stf R7,*AR1++(IR0) ;
;– – – – – – – – – – – –
sti R0,*AR0++(IR0) ; Store longs
|| sti R1,*AR1++(IR0) ;
sti R2,*AR0++(IR0) ;
|| sti R3,*AR1++(IR0) ;
sti R4,*AR0++(IR0) ;
|| sti R5,*AR1++(IR0) ;
sti R6,*AR0++(IR0) ;
|| sti R7,*AR1++(IR0) ;