Texas Instruments TMS320C3 Series, User Manual, Page: 39 / 166

DSK Hardware Interface
4-5 Functional Overview
4) The host drives the HPSTB signal high, indicating to the ’C31 that the data
is ready. The PAL detects the rising edge of HPSTB and drives the ’C31’s
READY signal low, unlocking (freeing) the locked-bus access, and con-
cluding the ’C31 read cycle.
5) This process is repeated until all four bytes are transferred (least signifi-
cant byte first). At each transfer, the ’C31 pieces the bytes together to form
a 32-bit word.
The host receives data in a similar manner:
1) The host waits for the HPACK signal, indicating that the ’C31 understands
the host request for a packet transfer.
2) The ’C31 starts a one-wait-state write access to location 0xFFF000. The
PAL decodes this address as the HPACK signal, drives the host’s ERROR
signal low, and drives the ’C31’s READY signal high. This prevents the
’C31 from completing its write access. The host uses the ERROR signal
to acknowledge that the ’C31 is already sending data.
3) When the host receives the HPIA signal, it drives PSTROBE low and the
host reads a byte or 4-bit nibble, depending on whether a bidirectional par-
allel printer is present in the host.
4) The host drives the HPSTB signal high, indicating to the ’C31 that the data
was read. The PAL detects the rising edge of HPSTB and drives the ’C31’s
READY signal low, concluding the ’C31 write cycle. This completes the
’C31 read cycle.
5) This process is repeated until all four bytes or eight nibbles are transferred
(least significant byte first). During each transfer, the host pieces the bytes
together to form a 32-bit word.
Note:
During the bootload process, the ’C31 does not read the third and fourth by-
tes of the first 32-bit word. The bootloader acts as if it is reading from an
EPROM and skips these bytes.