Texas Instruments TMS320C3 Series, User Manual, Page: 38 / 166

DSK Hardware Interface
4-4
Host communications
The host communicates with the ’C31 through the parallel printer port. The PC
manipulates the parallel port’s signals by writing to and reading from the host’s
parallel port control and status registers. Figure 4–2 and Figure 4–3 show the
parallel port control and status register bit fields used by the DSK host soft-
ware. (The labels below the printer port signal names refer to signal names as
used by the DSK board as shown in Figure 4–1.)
Figure 4–2. Parallel Port Control Register (0x37A)
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
7
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
6
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
5
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
4
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
3
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
2
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
1
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
0
Á
Á
Á ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁ
DIR0
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
DIR1
ÁÁÁÁ
ÁÁÁÁ
INT
ÁÁÁÁÁ
ÁÁÁÁÁ
SLCTIN
ÁÁÁÁ
ÁÁÁÁ
INIT
ÁÁÁÁÁ
ÁÁÁÁÁ
AUTOFD
ÁÁÁÁÁ
ÁÁÁÁÁ
PSTROBE
Á
Á ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
RESET
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
HPSTB
Á
Á ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
W
ÁÁÁÁ
ÁÁÁÁ
R/W
ÁÁÁÁÁ
ÁÁÁÁÁ
W
ÁÁÁÁ
ÁÁÁÁ
R/W
ÁÁÁÁÁ
ÁÁÁÁÁ
W
ÁÁÁÁÁ
ÁÁÁÁÁ
R/W
Á
Á
Figure 4–3. Parallel Port Status Register (0x379)
ÁÁ
ÁÁ
ÁÁ
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
7
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
6
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
5
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
4
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
3
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
2
ÁÁÁÁ
Á ÁÁ Á
ÁÁÁÁ
1
ÁÁÁÁÁ
Á ÁÁÁ Á
ÁÁÁÁÁ
0
Á
Á
Á
ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁ
BUSY
ÁÁÁÁÁ
ÁÁÁÁÁ
ACK
ÁÁÁÁ
ÁÁÁÁ
PAPER
ÁÁÁÁÁ
ÁÁÁÁÁ
SELECT
ÁÁÁÁ
ÁÁÁÁ
ERROR
ÁÁÁÁÁ
ÁÁÁÁÁ
ACK
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁÁÁ
ÁÁÁÁÁ
X
Á
Á ÁÁ
ÁÁ
ÁÁÁÁ
ÁÁÁÁ
D3
ÁÁÁÁÁ
ÁÁÁÁÁ
D2
ÁÁÁÁ
ÁÁÁÁ
D1
ÁÁÁÁÁ
ÁÁÁÁÁ
D0
ÁÁÁÁ
ÁÁÁÁ
HPACK
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Á
Á
The host initializes the ’C31 by pulsing the INIT signal (writes a 0 followed by
a 1 to the INIT bit field of the parallel port control register). This signal resets
the ’C31 and activates the bootload mode. The host then downloads your pro-
gram or the communications kernel to the ’C31. The parallel port is mapped
into the ’C31 memory to the address range 0xFFF000–0xFFFFFF, as shown
in Figure 4–4, page 4-7.
The host sends data to the ’C31 in the following way:
1) The host writes the byte to be transmitted to the I/O-mapped area of the
host’s parallel port data lines (I/O address 0x378 for LPT 1).
2) The host drives the HPSTB signal low and waits for an acknowledgement.
The HPSTB signal interrupts the ’C31 by pulsing the INT2 signal, indicat-
ing that the host is requesting the transfer of a packet. The INT2 signal is
needed only for the initial packet transfer request and is ignored during
subsequent packet requests.
3) The ’C31 starts a one-wait-state read access to location 0xFFF000. The
PAL decodes this address as the host interface active (HPACK) signal,
drives the host’s ERROR signal low, and drives the ’C31’s READY signal
high. This prevents the ’C31 from completing its read access. The host
uses the ERROR (HPACK) signal to acknowledge that the ’C31 is “locked”
and waiting to receive the data.