Texas Instruments LMK05028, Advance Information

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LMK05028
High-performance Network Synchronizer
Output
Dividers
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Sw
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Output
Buffers
6 8
4
Power
Conditioning
Device Control
I2C/SPI/Pin mode
EEPROM/ROM
TCXO/OCXO
(Optional)
PLL Core 1
PLL Core 2
XO
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
LMK05028
SNAS724 – FEBRUARY 2018
LMK05028 Low-Jitter Dual Channel Clock Synchronizer With Eight Outputs and Integrated
EEPROM
1
1 Features
1
• Two Independent PLL Cores, Each Featuring:
– Jitter: 150-fs RMS for Outputs ≥ 100 MHz
– Phase Noise: –102 dBc/Hz at 100-Hz Offset
for 122.88 MHz
– Hitless Switching: 50-ps Phase Transient With
Phase Cancellation
– Programmable Loop Bandwidth With Fastlock
– Standards-Compliant Synchronization and
Holdover Using a Low-Cost TCXO/OCXO
– Any Input to Any Output Frequency Translation
• Four Reference Clock Inputs
– Priority-Based Input Selection (Auto or
Manual)
– Digital Holdover on Loss of Reference
• Eight Clock Outputs With Programmable Drivers
– Up to Six Different Output Frequencies
– AC-LVDS, AC-CML, AC-LVPECL, HCSL, and
1.8-V or 2.5-V LVCMOS Output Formats
• EEPROM/ROM for Custom Startup Clock
Profiles
(2)
• Flexible Configuration Options
– 1 Hz (1 PPS) to 750 MHz on Input and Output
– XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
– DCO Mode: < 1 ppt/Step for Fine Frequency
and Phase Steering (IEEE 1588 Slave
Operation)
– Zero Delay for Deterministic Phase Offset
– Robust Clock Monitoring and Status
– I2C or SPI Interface
• Excellent Power Supply Noise Rejection
• Supply: 3.3-V Core With 1.8-V, 2.5-V, or 3.3-V
Output
• Industrial Temperature Range: –40°C to +85°C
2 Applications
• SyncE (G.8262), SONET/SDH (Stratum 3/3E,
G.813, GR-1244, GR-253), IEEE 1588 (PTP)
Slave Clock, or Optical Transport Network (G.709)
Synchronization
• Telecom and Enterprise Line Cards
• Wireless Base Station (BTS)
• Test and Measurement, Broadcast Video, and
Medical Ultrasound
• Jitter and Wander Attenuation, Precise Frequency
Translation, and Low-Jitter Clock Generation for
FPGA, DSP, ASIC, and CPU Devices.
3 Description
The LMK05028 device is a high-performance clock
generator, jitter cleaner, and clock synchronizer with
advanced
reference clock selection and hitless
switching to meet the stringent requirements of
communications infrastructure applications. The ultra-
low jitter reduces bit error rates (BER) in high-speed
serial links.
The device has two independent PLL cores that can
each synchronize or lock to one of four reference
clock inputs, and the LMK05028 can generate up to
eight
output clocks with up to six different
frequencies.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMK05028 VQFN (64) 9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Contact TI Field Sales to inquire about custom factory pre-
programmed devices.
LMK05028 Simplified Block Diagram