4.15 NAND Flash CS2 (CE0) 1-Bit ECC Register (NFECCCS2R)
SPRUGZ3A—May 2011
KeyStone Architecture External Memory Interface (EMIF16) User Guide
4-17
Chapter 4—Registers
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4.15 NAND Flash CS2 (CE0) 1-Bit ECC Register (NFECCCS2R)
The NAND Flash CS2 1-Bit ECC Register is used for NAND Flash connected to CE0.
It is shown in
and described in
.
Figure 4-11
NAND Flash CS2 (CE0) 1-Bit ECC Register (NFECCCS2R)
31
28
27
26
25
24
23
22
21
20
Reserved
p2048o
P1024o
P512o
P256o
P128o
P64o
P32o
P16o
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
19
18
17
16
15
12
11
10
9
8
p8o
p4o
p2o
p1o
Reserved
p2048o
P1024o
P512o
P256o
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
7
6
5
4
3
2
1
0
P128o
P64o
P32o
P16o
p8o
p4o
p2o
p1o
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
R - 0x0
Table 4-12
NAND Flash CS2 (CE0) 1-Bit ECC Register (NFECCCS2R) Details
Bit
Field
Reset Value
Description
31-28
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
27
p2048o
0x0
1-Bit ECC code calculated while reading/writing NAND Flash.
For 8-bit NAND Flash, p1o, p2o and p4o are column parities. p8o to p2048o are row parities.
For 16-bit NAND Flash, p1o, p2o, p4o and p8o are column parities. p16o to p2048o are row
parities.
26
p1024o
0x0
25
p512o
0x0
24
p256o
0x0
23
p128o
0x0
22
p64o
0x0
21
p32o
0x0
20
p16o
0x0
19
p8o
0x0
18
p4o
0x0
17
p2o
0x0
16
p1o
0x0
15-12
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
11
p2048e
0x0
1-Bit ECC code calculated while reading/writing NAND Flash.
For 8-bit NAND Flash, p1e, p2e and p4e are column parities. p8e to p2048e are row parities.
For 16-bit NAND Flash, p1e, p2e, p4e and p8e are column parities. p16e to p2048e are row
parities.
10
p1024e
0x0
9
p512e
0x0
8
p256e
0x0
7
p128e
0x0
6
p64e
0x0
5
p32e
0x0
4
p16e
0x0
3
p8e
0x0
2
p4e
0x0
1
p2e
0x0
0
p1e
0x0
End of Table 4-12