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4.11 Interrupt Mask Clear Register (IMCR)
SPRUGZ3A—May 2011
KeyStone Architecture External Memory Interface (EMIF16) User Guide
4-11
Chapter 4—Registers
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4.11 Interrupt Mask Clear Register (IMCR)
The Interrupt Mask Clear Register (IMCR) is shown in
.
Figure 4-7
Interrupt Mask Clear Register (IMCR)
31
6
5
2
1
0
Reserved
WR_MASK_CLR
Reserved
AT_MASK_CLR
R - 0x0
RW - 0x0
R - 0x0
RW - 0x0
Table 4-8
Interrupt Mask Clear Register (IMCR) Details
Bit
Field
Reset Value
Description
31-6
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect
5-2
WR_MASK_CLR
0x0
Mask clear for WR_MASKED bits in the Interrupt Masked Register.
Writing a 1 will disable the interrupts, and set these bits as well as the WR_MASK_SET bits in
the Interrupt Mask Set register. Writing a 0 has no effect.
1
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect
0
AT_MASK_CLR
0x0
Mask clear for AT_MASKED bit in the Interrupt Masked Register.
Writing a 1 will disable the interrupt, and set this bit as well as the AT_MASK_SET bit in the
Interrupt Mask Set register. Writing a 0 has no effect.
End of Table 4-8