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Texas Instruments EMIF16 User Manual Download Page 45

4.11 Interrupt Mask Clear Register (IMCR)

SPRUGZ3A—May 2011

KeyStone Architecture External Memory Interface (EMIF16) User Guide

4-11

Submit Documentation Feedback 

Chapter 4—Registers

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4.11 Interrupt Mask Clear Register (IMCR)

The Interrupt Mask Clear Register (IMCR) is shown in 

Figure 4-7

 and 

Table 4-8

.

Figure 4-7

Interrupt Mask Clear Register (IMCR)

31

6

5

2

1

0

Reserved

WR_MASK_CLR

Reserved

AT_MASK_CLR

R - 0x0

RW - 0x0

R - 0x0

RW - 0x0

Table 4-8

Interrupt Mask Clear Register (IMCR) Details

Bit

Field

Reset Value

Description

31-6

Reserved

0x0

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect

5-2

WR_MASK_CLR

0x0

Mask clear for WR_MASKED bits in the Interrupt Masked Register.

Writing a 1 will disable the interrupts, and set these bits as well as the WR_MASK_SET bits in 
the Interrupt Mask Set register. Writing a 0 has no effect.

1

Reserved

0x0

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect

0

AT_MASK_CLR

0x0

Mask clear for AT_MASKED bit in the Interrupt Masked Register.

Writing a 1 will disable the interrupt, and set this bit as well as the AT_MASK_SET bit in the 
Interrupt Mask Set register. Writing a 0 has no effect.

End of Table 4-8

Summary of Contents for EMIF16

Page 1: ...KeyStone Architecture Literature Number SPRUGZ3A May 2011 External Memory Interface EMIF16 User Guide ...

Page 2: ...i com SubmitDocumentationFeedback Release History Release Date Chapter Topic Description Comments Revision A May 2011 Introduction In the Features section updated the description of features not supported and added additional information about the 64MB limit 1 0 January 2011 All Initial Release ...

Page 3: ...nterface 2 4 2 5 1 EMIF16 Signal Description ASRAM NOR Flash 2 5 2 5 2 Programmable EMIF16 Parameters 2 6 2 5 3 EMIF16 Truth Table 2 6 2 5 4 Switching Waveforms 2 7 2 5 4 1 Asynchronous Reads 2 7 2 5 4 2 Asynchronous Writes 2 8 2 5 5 Select Strobe Mode 2 9 2 5 5 1 Asynchronous Reads in SS Mode 2 10 2 5 5 2 Asynchronous Writes in SS Mode 2 11 2 5 6 WE Strobe Mode 2 12 Chapter 3 Operating Modes 3 1 ...

Page 4: ... 4 12 4 13 NAND Flash Status Register NANDFSR 4 14 4 14 Page Mode Control Register PMCR 4 15 4 15 NAND Flash CS2 CE0 1 Bit ECC Register NFECCCS2R 4 17 4 16 NAND Flash CS3 CE1 1 Bit ECC Register NFECCCS3R 4 18 4 17 NAND Flash CS4 CE2 1 Bit ECC Register NFECCCS4R 4 18 4 18 NAND Flash CS5 CE3 1 Bit ECC Register NFECCCS5R 4 18 4 19 NAND Flash 4 Bit ECC Load Register NANDF4BECCLR 4 18 4 20 NAND Flash 4...

Page 5: ...IMR Description 4 9 Table 4 7 Interrupt Mask Set Register IMSR Description 4 10 Table 4 8 Interrupt Mask Clear Register IMCR Description 4 11 Table 4 9 NAND Flash Control Register NANDFCR Description 4 12 Table 4 10 NAND Flash Status Register NANDFSR Description 4 14 Table 4 11 Page Mode Control Register PMCR Description 4 15 Table 4 12 NAND Flash CS2 CE0 1 Bit ECC Register NFECCCS2R Description 4...

Page 6: ...ycle Config Register 4 4 Figure 4 3 Async 1 Config Register A1CR 4 6 Figure 4 4 Interrupt Raw Register IRR 4 8 Figure 4 5 Interrupt Masked Register IMR 4 9 Figure 4 6 Interrupt Mask Set Register IMSR 4 10 Figure 4 7 Interrupt Mask Clear Register IMCR 4 11 Figure 4 8 NAND Flash Control Register NANDFCR 4 12 Figure 4 9 NAND Flash Status Register NANDFSR 4 14 Figure 4 10 Page Mode Control Register PM...

Page 7: ...d keywords are in boldface font Arguments for which you supply values are in italic font Terminal sessions and information the system displays are in screen font Information you must enter is in boldface screen font Elements in square brackets are optional Notes use the following conventions Note Means reader take note Notes contain helpful suggestions or references to material not covered in the ...

Page 8: ... from Texas Instruments Trademarks All brand names and trademarks mentioned in this document are the property of Texas Instruments Incorporated or their respective owners as applicable TMS320C6000 DSP and Instruction Set Reference Guide SPRU189 TMS320C6000 Programmer s Guide SPRU198 TMS320C6000 Code Composer Studio Forum Forum C66x CorePac User Guide SPRUGW0 ...

Page 9: ...er 1 Introduction This manual describes the External Memory Interface peripheral utilizing a 16 bit bus EMIF16 This manual describes the purpose features architecture operating modes and registers of the EMIF16 This chapter provides the following information 1 1 Purpose of the Peripheral on page 1 2 1 2 Features on page 1 2 ...

Page 10: ...e over 4 chip selects 8 bit and 16 bit data widths Programmable cycle timings for each chip select Extended wait support if available model supports Select Strobe mode support if available model supports Page Burst mode read support for NOR Flash 1 bit ECC for 8 bit and 16 bit NAND Flash Does not support error correction 4 bit ECC for 8 bit and 16 bit NAND Flash Does not support error correction B...

Page 11: ...mentation Feedback Chapter 2 Architecture This chapter contains the following topics 2 1 EMIF16 Signal Descriptions on page 2 2 2 2 Memory Organization on page 2 3 2 3 Supported Modes on page 2 3 2 4 Configuring the EMIF16 for Asynchronous Access on page 2 3 2 5 ASRAM NOR Flash Interface on page 2 4 ...

Page 12: ...data writes EMIFA 23 0 External address output EMIFCE0 External CE0 chip select Active low chip select for CE space 0 EMIFCE1 External CE1 chip select Active low chip select for CE space 1 EMIFCE2 External CE2 chip select Active low chip select for CE space 2 EMIFCE3 External CE3 chip select Active low chip select for CE space 3 EMIFBE 1 0 Byte enables EMIFWAIT 1 0 Used to insert wait states into ...

Page 13: ...access The main advantage of this mode is that it allows two 8 bit devices to be connected to the same chip select In this mode the bytes enables are connected to the write strobes of the two 8 bit devices WE strobe mode is the default mode supported on CE3 WE strobe mode is not supported for CE0 2 The Select Strobe SS mode is activated by setting the ss bit in the Async Config Register for the ch...

Page 14: ... 2 5 ASRAM NOR Flash Interface EMIF16 connection diagrams for 16 bit and 8 bit SRAM NOR Flash connected to chip select0 are shown in Figure 2 2 Figure 2 3 respectively Figure 2 2 Connecting to 16 bit ASRAM see note below EMIFD 15 0 EMIFA 22 0 23 CE0 EMIFBE1 External Memory Interface EMIF16 EMIFWE EMIFOE WAIT 1 0 I O 15 0 A N 0 SRAM NOR Flash CS 2N 1 x 16 UB WE OE Vcc LB EMIFBE0 ...

Page 15: ...Figure 2 5 show reads and writes initiated by different control signals EMIFD 7 0 EMIFA 21 0 23 22 CE0 EMIFBE1 External Memory EMIFWE Interface EMIF16 EMIFOE WAIT 1 0 I O 7 0 A N 0 SRAM NOR Flash CS 2N 1 x 8 LB WE OE Vcc X EMIFBE0 Table 2 2 ASRAM NOR Flash Interface Signals EMIF16 Pin ASRAM Pin Description EMIFD 15 0 EMIFD 7 0 I O 15 0 I O 7 0 Data I O pins 16 8 bit bidirectional data path for I O...

Page 16: ... end of the cycle which may be either an address change or the deactivation of the chip select signal Minimum value is 1 0 treated as 1 Turnaround Cycles between the end of one asynchronous memory access and the start of another asynchronous memory access minus one cycle This delay is not incurred between a read followed by read or a write followed by a write to same chip select Data width Width o...

Page 17: ...H Data is sampled on clock rising edge concurrent with the beginning of the hold period and end of strobe At the end of the hold period EMIFCE goes inactive HIGH only if no read write access to the chip select space is still pending EMIFBE 1 0 become inactive Address on address lines EMIFA 23 0 become invalid Note 1 In case an asynchronous request cannot be serviced in a single asynchronous access...

Page 18: ...UP W_STROBE and W_HOLD values programmed in the Async 1 2 3 4 Config Register EMIFCE becomes active if not already active from a previous access EMIFBE 1 0 become valid Address on address lines on EMIFA 23 0 become valid Data on EMIFD 15 0 is driven EMIFRnW becomes active LOW At the start of the strobe period EMIFWE becomes active At the start of the hold period EMIFWE becomes inactive At the end ...

Page 19: ...ring turnaround cycles Note 2 If the entire read or write access has completed and there are more requests pending the EMIF16 enters turnaround state and waits for programmed turnaround cycles Figure 2 5 shows a write cycle initiated as described above Refer to the device datasheet for timing characteristics Figure 2 5 Asynchronous Write Timing Diagram 2 5 5 Select Strobe Mode The Select Strobe SS...

Page 20: ...t the start of the hold period EMIFCE and EMIFOE become inactive HIGH Data is sampled on clock rising edge concurrent with the beginning of the hold period and end of strobe At the end of the hold period EMIFBE 1 0 become inactive Address on address lines EA 23 0 become invalid Note 1 In case an asynchronous request cannot be serviced in a single asynchronous access cycle multiple cycles will be n...

Page 21: ...W becomes active LOW At the start of the strobe period EMIFCE and EMIFWE become active At the start of the hold period EMIFCE and EMIFWE become inactive At the end of the hold period Address on address lines EMIFA 23 0 become invalid EMIFD 15 0 becomes invalid Note 1 In case an asynchronous request cannot be serviced in a single asynchronous access cycle multiple cycles will be needed to complete ...

Page 22: ...ng specifications Figure 2 7 Write Cycle Select Strobe Mode 2 5 6 WE Strobe Mode In the WE strobe mode Figure 2 8 the byte enables act as write strobes This mode is useful for combining two 8 bit devices to create a 16 bit data bus allowing the EMIF16 to perform byte writes to two 8 bit devices which do not have byte enable inputs In WE strobe mode the byte enables are connected to the write strob...

Page 23: ...cture www ti com Figure 2 8 Asynchronous Writes WE Strobe Mode Figure 2 9 Asynchronous Reads WE Strobe Mode EMIFCE EMIFBE 1 0 EMIFA 23 0 Byte write strobe Address Write data EMIFD 15 0 EMIFOE EMIFWE EMIFRnW Write setup Write strobe Write hold EMIFCE EMIFBE 1 0 EMIFA 23 0 Byte enables Address Read data EMIFD 15 0 EMIFOE EMIFWE EMIFRnW Read setup Read strobe Read hold ...

Page 24: ...2 5 ASRAM NOR Flash Interface 2 14 KeyStone Architecture External Memory Interface EMIF16 User Guide SPRUGZ3A May 2011 SubmitDocumentationFeedback Chapter 2 Architecture www ti com ...

Page 25: ...ing EMIF16 in NAND Flash Mode on page 3 3 3 3 EMIF16 Signal Description NAND Flash on page 3 3 3 4 Using ALE and CLE on page 3 4 3 5 NAND Read and Program Operations on page 3 4 3 6 Checking the Status of Operation on page 3 5 3 7 ECC Support on page 3 5 3 8 Extended Wait Mode on page 3 9 3 9 Data Bus Parking on page 3 9 3 10 Interrupt Support on page 3 9 3 11 NOR Flash Page Mode on page 3 10 3 12...

Page 26: ...me See Section 3 7 for details on ECC functionality and support A NAND access cycle consists of command address and data phases in order to complete a NAND Flash transfer All NAND Flash operations can be divided into single asynchronous cycles which can be executed using software The following sections describe connecting to a NAND Flash device configuring EMIF16 registers for NAND Flash mode comm...

Page 27: ...hip Select CS Write Enable WE and Read Enable RE are used by the NAND to distinguish between command address and data read write phases Table 3 1 describes signals that define the NAND Flash interface Table 3 1 NAND interface signal description NAND Flash Pin Type Description ALE Input During the time ALE is HIGH address information is transferred from EMIFD 7 0 to on chip address register upon a ...

Page 28: ...riod between two asynchronous cycles After a read command is issued it takes time tR for the read data to be driven on the IO pins Note Since chip select is inactive during this time EMIF16 does not support NAND devices that require the chip select to be low during tR Each NAND operation starts off with issuing a command cycle The command is placed on EMIFD 7 0 chip select EMIFCE is driven low and...

Page 29: ...cted to a specific chip select is set off by writing a 1 to the CSN_ECC_START bit of the NAND Flash Control Register NANDFCR 1 bit ECC calculation for each chip select is independent of other chip selects Once the 1 bit ECC is calculated for a chip select it can be read from the corresponding chip select s NAND Flash 1 bit ECC Register Reading this register clears the CSN_ECC_START bit Software is...

Page 30: ...registers the 4BIT_ECC_START bit is cleared The contents of NAND Flash 4 Bit ECC 1 4 registers are cleared when 4 bit ECC calculation is started by setting 4BIT_ECC_START The 4 bit ECC algorithm uses 10 bits 4 bit ECC calculation in EMIF16 however uses 8 bit values for both 8 bit and 16 bit devices The 8 bit value is converted to 10 bits and the upper 2 bits of the 10 bit value are zeroed out by E...

Page 31: ...e NAND Flash Control Register to 1 2 Perform Read Read 518 Bytes of data from NAND Flash 3 Clear 4BIT_ECC_START bit Clear 4BIT_ECC_START bit in NANDFCR by reading any of the NAND Flash 4 Bit ECC registers 4 Read Parity Read parity stored in the spare location of NAND Flash 5 8 Bit or 16 Bit to 10 Bit conversion Convert 8 or 16 bit parity values to 10 bits This can be accomplished by concatenating ...

Page 32: ... 0x3 Error correction complete error exists 11 Read number of errors The field ERR_NUM in NAND Flash Status Register gives the number of errors 12 Read Error Address Error address can be read from NAND Flash Error Address 1 2 Registers Address for the errored word is equal to Total words read 7 Address value So for 518 Bytes the address will be 518 7 address value or 525 address value 13 Read Erro...

Page 33: ...ter on maximum number of clock cycles expires EMIF16 proceeds to the hold period regardless of the state of the EMIFWAIT pin For details on AWCCR refer to Section 4 3 The expiration of the counter can also be used to set an asynchronous timeout interrupt For details on how to enable this interrupt refer to Section 3 10 Note In Extended Wait Mode strobe parameters R_STROBE and W_STROBE must not be ...

Page 34: ...synchronous memory timings must be programmed in the Async Config Register For Program Erase operations and memory organization refer to the NOR device datasheet 3 12 Reset Considerations EMIF16 has two active low resets Power up reset that resets both the state machine and internal registers Soft reset that only resets the state machine and does not reset internal registers except for interrupt r...

Page 35: ...ash Status Register NANDFSR on page 4 14 4 14 Page Mode Control Register PMCR on page 4 15 4 15 NAND Flash CS2 CE0 1 Bit ECC Register NFECCCS2R on page 4 17 4 16 NAND Flash CS3 CE1 1 Bit ECC Register NFECCCS3R on page 4 18 4 17 NAND Flash CS4 CE2 1 Bit ECC Register NFECCCS4R on page 4 18 4 18 NAND Flash CS5 CE3 1 Bit ECC Register NFECCCS5R on page 4 18 4 19 NAND Flash 4 Bit ECC Load Register NANDF...

Page 36: ...CR Async 2 Config Register 4 5 18h A3CR Async 3 Config Register 4 6 1Ch A4CR Async 4 Config Register 4 7 40h IRR Interrupt Raw Register 4 8 44h IMR Interrupt Masked Register 4 9 48h IMSR Interrupt Mask Set Register 4 10 4Ch IMCR Interrupt Mask Clear Register 4 11 60h NANDFCR NAND Flash Control Register 4 12 64h NANDFSR NAND Flash Status Register 4 13 68h PMCR Page Mode Control Register 4 14 70h NF...

Page 37: ...1 Refer to the device specific datasheet for the register value for your device Figure 4 1 Revision Code and Status Register 31 30 29 16 15 8 7 0 BE Reserved MODULE_ID MJ_REV MIN_REV R R R R R Table 4 2 Revision Code and Status Register RCSR Details Bit Field Reset Value Description 31 BE Defines EMIF16 endianness 0 Little Endian 1 Big Endian 30 Reserved 0x0 Reserved The reserved bit location is a...

Page 38: ...eserved 0x1 Reserved The reserved bit location is always read as 1 30 Reserved 0x1 Reserved The reserved bit location is always read as 1 29 WP1 0x1 Defines the wait polarity for WAIT 1 0 Wait if WAIT 1 is low 1 Wait if WAIT 1 is high 28 WP0 0x1 Defines the wait polarity for WAIT 0 0 Wait if WAIT 0 is low 1 Wait if WAIT 0 is high 27 24 Reserved 0x0 Reserved The reserved bit location is always read...

Page 39: ...om 15 8 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 0 MAX_EXT_WAIT 0x80 Maximum extended wait cycles EMIF16 will wait for MAX_EXT_WAIT 1 x 16 cycles before an extended asynchronous cycles is terminated End of Table 4 3 Table 4 3 Async Wait Cycle Config Register AWCCR Details Part 2 of 2 Bit Field Reset Value Description ...

Page 40: ...TUP 0xF Write Strobe Setup cycles Number of EMIF16 clock cycles from EMIFA 23 0 EMIFD 15 0 EMIFBE 1 0 and CE being set to EMIFWE asserted minus one cycle The reset value is 16 cycles 25 20 W_STROBE 0x3F Write Strobe Duration cycles Number of EMIF16 clock cycles for which EMIFWE is held active minus one cycle The reset value is 64 cycles This field cannot be zero when EW 1 19 17 W_HOLD 0x7 Write St...

Page 41: ... 4 Config Register A4CR Bit fields and their operation are exactly the same as A1CR except that programmed values will be applied for CE3 3 2 TA 0x3 Turn Around cycles Number of EMIF16 clock cycles between the end of one asynchronous memory access and the start of another asynchronous memory access minus one cycle This delay is not incurred between a read followed by a read or a write followed by ...

Page 42: ...s 0 A value written to this field has no effect 5 2 WR 0x0 Wait Rise Set to 1 by hardware to indicate rising edge on the corresponding EMIFWAIT pin has been detected The WP0 1 bits in the Async Wait Cycle Config register have no effect on these bits Writing a 1 will clear these bits as well as the WR_MASKED bits in the Interrupt Masked register Writing a 0 has no effect 1 Reserved 0x0 Reserved The...

Page 43: ...dge on the corresponding WAIT pin has been detected only if WR_MASK_SET bit has been set in Interrupt Mask Set Register The WP0 1 bits in the Async Wait Cycle Config register have no effect on these bits Writing a 1 will clear these bits as well as the WR bits in the Interrupt Raw register Writing a 0 has no effect 1 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value writt...

Page 44: ... 31 6 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 5 2 WR_MASK_SET 0x0 Mask set for WR_MASKED bits in the Interrupt Masked Register Writing a 1 will enable the interrupts and set these bits as well as the WR_MASK_CLR bits in the Interrupt Mask Clear register Writing a 0 has no effect 1 Reserved 0x0 Reserved The reserved bit locatio...

Page 45: ...ption 31 6 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 5 2 WR_MASK_CLR 0x0 Mask clear for WR_MASKED bits in the Interrupt Masked Register Writing a 1 will disable the interrupts and set these bits as well as the WR_MASK_SET bits in the Interrupt Mask Set register Writing a 0 has no effect 1 Reserved 0x0 Reserved The reserved bit l...

Page 46: ...12 4BIT_ECC_START 0x0 NAND Flash 4 bit ECC start for the selected chip select Set to 1 to start 4 bit ECC calculation on data for NAND Flash on chip select selected by 4BIT_ECC_SEL This bit is cleared when any of the NAND Flash 4 Bit ECC registers are read Writing a 0 has no effect 11 CS5_ECC_START 0x0 NAND Flash 1 bit ECC start for chip select CE3 Set to 1 to start 1 bit ECC calculation on data f...

Page 47: ...x1 Selects chip select CE1 0x2 Selects chip select CE2 0x3 Selects chip select CE3 3 CS5_USE_NAND 0x0 NAND Flash mode for chip select CE3 Set to 1 if using NAND Flash on CE3 2 CS4_USE_NAND 0x0 NAND Flash mode for chip select CE2 Set to 1 if using NAND Flash on CE2 1 CS3_USE_NAND 0x0 NAND Flash mode for chip select CE1 Set to 1 if using NAND Flash on CE1 0 CS1_USE_NAND 0x0 NAND Flash mode for chip ...

Page 48: ...calculation is done 0x0 1 error found 0x1 2 errors found 0x2 3 errors found 0x3 4 errors found 15 12 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 8 CORR_STATE 0x0 4 bit ECC state value when performing error address and error value calculation 0x0 No error 0x1 Errors cannot be corrected five or more errors The number of errors ca...

Page 49: ...Flash connected on CE3 0x1 8 word page 0x0 4 word page 24 CS5_PG_MD_EN Page Mode enable for NOR Flash connected on CE3 0x1 Use page mode 0x0 Disable page mode 23 18 CS4_PG_DEL 0x3F Page access delay for NOR Flash connected on CE2 Number of EMIF16 clock cycles required for the page read data to be valid minus one cycle This value must not be set to 0 17 CS4_PG_SIZE Page Size for NOR Flash connected...

Page 50: ...nFeedback Chapter 4 Registers www ti com 1 CS2_PG_SIZE Page Size for NOR Flash connected on CE0 0x1 8 word page 0x0 4 word page 0 CS2_PG_MD_EN Page Mode enable for NOR Flash connected on CE0 0x1 Use page mode 0x0 Disable page mode End of Table 4 11 Table 4 11 Page Mode Control Register PMCR Details Part 2 of 2 Bit Field Reset Value Description ...

Page 51: ... NFECCCS2R Details Bit Field Reset Value Description 31 28 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 p2048o 0x0 1 Bit ECC code calculated while reading writing NAND Flash For 8 bit NAND Flash p1o p2o and p4o are column parities p8o to p2048o are row parities For 16 bit NAND Flash p1o p2o p4o and p8o are column parities p16o t...

Page 52: ...lash CS5 CE3 1 Bit ECC Register NFECCCS5R The NAND Flash CS5 1 Bit ECC Register is exactly the same as NAND Flash CS2 1 Bit ECC Register only difference being the former is used for device on CE3 4 19 NAND Flash 4 Bit ECC Load Register NANDF4BECCLR The NAND Flash 4 Bit ECC Load Register is shown in Figure 4 12 and described in Table 4 13 Figure 4 12 NAND Flash 4 Bit ECC Load Register NANDF4BECCLR ...

Page 53: ...0 Reserved 4BIT_ECC_VAL2 Reserved 4BIT_ECC_VAL1 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 14 NAND Flash 4 Bit ECC 1 Register NANDF4BECC1R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 4BIT_ECC_VAL2 0x0 4 Bit ECC or syndrome value 2 calculated while writing or reading NAND Flash 15 10 Reserved 0x...

Page 54: ... Reserved 4BIT_ECC_VAL4 Reserved 4BIT_ECC_VAL3 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 15 NAND Flash 4 Bit ECC 2 Register NANDF4BECC2R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 4BIT_ECC_VAL4 0x0 4 Bit ECC or syndrome value 4 calculated while writing or reading NAND Flash 15 10 Reserved 0x0...

Page 55: ...0 Reserved 4BIT_ECC_VAL6 Reserved 4BIT_ECC_VAL5 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 16 NAND Flash 4 Bit ECC 3 Register NANDF4BECC3R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 4BIT_ECC_VAL6 0x0 4 Bit ECC or syndrome value 6 calculated while writing or reading NAND Flash 15 10 Reserved 0x...

Page 56: ... Reserved 4BIT_ECC_VAL8 Reserved 4BIT_ECC_VAL7 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 17 NAND Flash 4 Bit ECC 4 Register NANDF4BECC4R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 4BIT_ECC_VAL8 0x0 4 Bit ECC or syndrome value 8 calculated while writing or reading NAND Flash 15 10 Reserved 0x0...

Page 57: ...NAND Flash Error Address 1 Register NANDFEA1R 31 26 25 16 15 10 9 0 Reserved ERR_ADDR2 Reserved ERR_ADDR1 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 18 NAND Flash Error Address 1 Register NANDFEA1R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 ERR_ADDR2 0x0 4 Bit error address 2 15 10 Reserved 0x...

Page 58: ...AND Flash Error Address 2 Register NANDFEA2R 31 26 25 16 15 10 9 0 Reserved ERR_ADDR4 Reserved ERR_ADDR3 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 19 NAND Flash Error Address 2 Register NANDFEA2R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 ERR_ADDR4 0x0 4 Bit error address 4 15 10 Reserved 0x0...

Page 59: ...19 NAND Flash Error Value 1 Register NANDFEV1R 31 26 25 16 15 10 9 0 Reserved ERR_VAL2 Reserved ERR_VAL1 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 20 NAND Flash Error Value 1 Register NANDFEV1R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 ERR_VAL2 0x0 4 Bit error value 2 15 10 Reserved 0x0 Rese...

Page 60: ...0 NAND Flash Error Value 2 Register NANDFEV2R 31 26 25 16 15 10 9 0 Reserved ERR_VAL4 Reserved ERR_VAL3 R 0x0 R 0x0 R 0x0 R 0x0 Table 4 21 NAND Flash Error Value 2 Register NANDFEV2R Details Bit Field Value Description 31 26 Reserved 0x0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 ERR_VAL4 0x0 4 Bit error value 4 15 10 Reserved 0x0 Reser...

Page 61: ...ons 4 2 Block Diagram 2 2 boot memory for 1 2 modes 1 2 Bus contention 2 12 byte enables 2 12 C chip select 1 2 2 3 2 6 3 2 to 3 4 CLE 3 4 clock 3 4 cycles 2 3 3 9 cycles max number 3 9 clocking 2 3 command cycle 3 4 phase 3 4 register 3 4 Command Latch Enable 3 3 configuring EMIF16 registers 3 2 Connecting to NAND Flash 3 2 control signals 2 5 to 2 6 3 3 cycle timings 1 2 D data bus 2 6 2 12 bus ...

Page 62: ... operation 3 4 NAND Flash device connecting 3 2 NAND Flash interface signals 3 3 NAND mode configuring 3 3 NANDFCR 3 6 NANDFSR 3 5 NOR Flash Page Mode 3 10 O operating modes 2 3 Operation Status 3 5 P Page Mode Control Register 3 10 Page Burst mode 1 2 PMCR 3 10 programmable parameters 2 6 R R_STROBE 3 9 read cycle time 2 6 Read Enable 3 3 read write cycles 2 5 register fields 4 2 resets 3 10 S Se...

Page 63: ...horized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge ...

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