![background image](http://html.mh-extra.com/html/texas-instruments/emif16/emif16_user-manual_1097088047.webp)
4.12 NAND Flash Control Register (NANDFCR)
SPRUGZ3A—May 2011
KeyStone Architecture External Memory Interface (EMIF16) User Guide
4-13
Chapter 4—Registers
www.ti.com
5-4
4BIT_ECC_SEL
0x0
NAND Flash 4-bit ECC chip select selection. This field selects the chip select on which the
4-bit ECC will be calculated.
0x0 - Selects chip select CE0.
0x1 - Selects chip select CE1.
0x2 - Selects chip select CE2.
0x3 - Selects chip select CE3.
3
CS5_USE_NAND
0x0
NAND Flash mode for chip select CE3.
Set to 1 if using NAND Flash on CE3.
2
CS4_USE_NAND
0x0
NAND Flash mode for chip select CE2.
Set to 1 if using NAND Flash on CE2.
1
CS3_USE_NAND
0x0
NAND Flash mode for chip select CE1.
Set to 1 if using NAND Flash on CE1.
0
CS1_USE_NAND
0x0
NAND Flash mode for chip select CE0.
Set to 1 if using NAND Flash on CE0
End of Table 4-9
Table 4-9
NAND Flash Control Register (NANDFCR) Details (Part 2 of 2)
Bit
Field
Reset Value
Description