![background image](http://html.mh-extra.com/html/texas-instruments/emif16/emif16_user-manual_1097088043.webp)
4.9 Interrupt Masked Register (IMR)
SPRUGZ3A—May 2011
KeyStone Architecture External Memory Interface (EMIF16) User Guide
4-9
Chapter 4—Registers
www.ti.com
4.9 Interrupt Masked Register (IMR)
The Interrupt Masked Register (IMR) is shown in
and
Figure 4-5
Interrupt Masked Register (IMR)
31
6
5
2
1
0
Reserved
WR_MASKED
Reserved
AT_MASKED
R - 0x0
RW - 0x0
R - 0x0
RW - 0x0
Table 4-6
Interrupt Masked Register (IMR) Details
Bit
Field
Reset Value
Description
31-6
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect
5-2
WR_MASKED
0x0
Masked Wait Rise.
Set to 1 by hardware to indicate rising edge on the corresponding WAIT pin has been detected
only if WR_MASK_SET bit has been set in Interrupt Mask Set Register. The WP0-1 bits in the Async
Wait Cycle Config register have no effect on these bits.
Writing a 1 will clear these bits as well as the WR bits in the Interrupt Raw register. Writing a 0 has
no effect.
1
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect
0
AT_MASKED
0x0
Masked Asynchronous Timeout.
Set to 1 by hardware to indicate that during an extended asynchronous memory access cycle, the
WAIT signal did not go inactive within the number of cycles defined by the MAX_EXT_WAIT field in
Async Wait Cycle Config register, only if AT_MASK_SET is set in Interrupt Mask Set Register.
Writing a 1 will clear this bit as well as the AT bit in the Interrupt Raw register. Writing a 0 has no
effect.
End of Table 4-6