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3.4 Using ALE and CLE
3-4
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 3—Operating Modes
www.ti.com
3.4 Using ALE and CLE
If using EMIFA11 and EMIFA12 as ALE and CLE respectively for CE0, choose the
following addresses. The base address for CE0 space is 0x70000000.
The base addresses for chip selects CE1, CE2 and CE3 are 0x7400 0000, 0x7800 0000
and 0x7C00 0000 respectively. The addresses for ALE and CLE can thus be derived for
CE1-3 spaces as well.
During the command phase, a command on EMIFD[7:0] is latched into the device’s
internal command register. During the address phase, an address on EMIFD[7:0] is
latched into the device’s internal address register. During the data phase, data on
EMIFD[15:0] is read out off or latched into the device’s internal data register for reads
and writes respectively.
3.5 NAND Read and Program Operations
A NAND access cycle is composed of multiple single asynchronous cycles that must be
executed by software. The chip select does not remain active for the entire duration of
the access, but becomes inactive during the period between two asynchronous cycles.
After a read command is issued, it takes time t
R
for the read data to be driven on the IO
pins.
Note—
Since chip select is inactive during this time, EMIF16 does not support
NAND devices that require the chip select to be low during t
R
.
Each NAND operation starts off with issuing a command cycle. The command is
placed on EMIFD[7:0], chip select EMIFCE is driven low and CLE goes high. Write
enable EMIFWE behaves as a clock – commands, address, or data are clocked into the
NAND device on the rising edge of EMIFWE.
Most commands require multiple address cycles followed by a second command cycle.
While the NAND is busy carrying out a Program/Erase operation a new command
should not be issued until the NAND device is ready to accept new commands. See
for details. The exceptions to this are the RESET and READ STATUS
commands which can be issued even when the NAND device is busy. The READ
STATUS command is used to obtain the ‘ready’ status of the device.
For specific details on command cycle, address cycles, and data read/write phases refer
to the device datasheet.
Table 3-2
CE0 Addressing when EMIFA11 and EMIFA12 are used as ALE and CLE
respectively
Address
ALE
CLE
Phase
0x7000 0000
LOW
LOW
Data Phase
0x7000 2000
HIGH
LOW
Address Phase
0x7000 4000
LOW
HIGH
Command Phase
End of Table 3-2