4.3 Async Wait Cycle Config Register (AWCCR)
4-4
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 4—Registers
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4.3 Async Wait Cycle Config Register (AWCCR)
The Async Wait Cycle Config Register is as shown in
Figure 4-2
Async Wait Cycle Config Register
31
30
29
28
27
24 23
22 21
20
Reserved
Reserved
WP1
WP0
Reserved
CS5_WAIT
CS4_WAIT
RW - 0x1
RW - 0x1
RW - 0x1
RW - 0x1
R - 0x0
RW
RW
19
18 17
16 15
8 7
0
CS3_WAIT
CS2_WAIT
Reserved
MAX_EXT_WAIT
RW
RW
R-0x0
RW-0x80
Table 4-3
Async Wait Cycle Config Register (AWCCR) Details (Part 1 of 2)
Bit
Field
Reset Value
Description
31
Reserved
0x1
Reserved. The reserved bit location is always read as 1.
30
Reserved
0x1
Reserved. The reserved bit location is always read as 1.
29
WP1
0x1
Defines the wait polarity for WAIT[1]
0 – Wait if WAIT[1] is low
1 – Wait if WAIT[1] is high
28
WP0
0x1
Defines the wait polarity for WAIT[0]
0 – Wait if WAIT[0] is low
1 – Wait if WAIT[0] is high
27-24
Reserved
0x0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
23-22
CS5_WAIT
WAIT map bits for CE3:
0x0 – WAIT[0] is used.
0x1 – WAIT[1] is used.
0x2 – Reserved.
0x3 – Reserved.
21-20
CS4_WAIT
WAIT map bits for CE2:
0x0 – WAIT[0] is used.
0x0 – WAIT[1] is used.
0x0 – Reserved.
0x0 – Reserved.
19-18
CS3_WAIT
WAIT map bits for CE1:
0x0 – WAIT[0] is used.
0x0 – WAIT[1] is used.
0x0 – Reserved.
0x0 – Reserved.
17-16
CS2_WAIT
WAIT map bits for CE0:
0x0 – WAIT[0] is used.
0x0 – WAIT[1] is used.
0x0 – Reserved.
0x0 – Reserved.