![background image](http://html.mh-extra.com/html/texas-instruments/emif16/emif16_user-manual_1097088026.webp)
3.1 NAND Flash Mode
3-2
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 3—Operating Modes
www.ti.com
3.1 NAND Flash Mode
EMIF16 supports NAND Flash mode. To enable NAND flash mode, the corresponding
chip select’s
csN_use_nand
bit must be set in the NAND Flash Control Register
(NANDFCR). The NAND Flash timing values must be programmed in the chip select’s
Async Configuration Register. For more details on these registers refer to
NAND Flash mode also supports both 1-bit and 4-bit error correction code (ECC)
calculation. 4-bit ECC can only be used for one chip select at a time. See
for
details on ECC functionality and support.
A NAND access cycle consists of command, address and data phases in order to
complete a NAND Flash transfer. All NAND Flash operations can be divided into
single asynchronous cycles which can be executed using software.
The following sections describe connecting to a NAND Flash device, configuring
EMIF16 registers for NAND Flash mode, command set, ECC support and so on.
3.1.1 Connecting to NAND Flash
and
show how to connect to 8-bit and 16-bit NAND Flash
respectively.
Figure 3-1
Connecting to 8-bit NAND Flash
Figure 3-2
Connecting to 16-bit NAND Flash
EMIFA12
EMIFA11
EMIFCE
EMIFWE
EMIFOE
EMIFD[7:0]
EMIFWAIT
CLE
ALE
CS#
WE#
RE#
IO[7:0]
R/B#
EMIF16
NAND
Flash
8-bit
EMIFA12
EMIFCE
EMIFWE
EMIFOE
EMIFD[5:0]
EMIFWAIT
CLE
ALE
CS#
WE#
RE#
IO[15:0]
R/B#
EMIF16
NAND
Flash
16-bit
EMIFA11