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2.5 ASRAM/NOR Flash Interface
2-10
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 2—Architecture
www.ti.com
2.5.5.1 Asynchronous Reads in SS Mode
An asynchronous read cycle in SS mode proceeds as follows (see
1, 2 below):
•
At the start of the setup period:
–
Setup, strobe and hold values are set according to the R_SETUP, R_STROBE
and R_HOLD values programmed in the Async 1/2/3/4 Config Register
–
EMIFBE[1:0] become active (LOW) as byte enables
–
Address on address lines EMIFA[23:0] become valid
•
At the start of the strobe period, EMIFCE and EMIFOE become active (LOW) at
the same time.
•
At the start of the hold period:
–
EMIFCE and EMIFOE become inactive (HIGH).
–
Data is sampled on clock rising edge concurrent with the beginning of the
hold period (and end of strobe)
•
At the end of the hold period:
–
EMIFBE[1:0] become inactive.
–
Address on address lines EA[23:0] become invalid.
Note—
1: In case an asynchronous request cannot be serviced in a single
asynchronous access cycle, multiple cycles will be needed to complete the
single read or write request. In this case, the EMIF16 enters the setup phase
directly without incurring turnaround cycles.
Note—
2: If the entire read or write access has completed and there are more
requests pending, the EMIF16 enters turnaround state and waits for
programmed turnaround cycles.
shows the switching waveform for asynchronous reads in SS mode. Refer to
the device datasheet for device timing specifications.