![background image](http://html.mh-extra.com/html/texas-instruments/emif16/emif16_user-manual_1097088012.webp)
2.1 EMIF16 Signal Descriptions
2-2
KeyStone Architecture External Memory Interface (EMIF16) User Guide
SPRUGZ3A—May 2011
Chapter 2—Architecture
www.ti.com
2.1 EMIF16 Signal Descriptions
A basic block diagram of the EMIF16 asynchronous interface is shown in
.
below lists the asynchronous signals of the EMIF16 module.
Figure 2-1
Basic Block diagram for EMIF16
Table 2-1
EMIF16 Signal Descriptions
Pin
Description
EMIFD [15:0]
Data I/O. Input for data reads and output for data writes.
EMIFA [23:0]
External address output.
EMIFCE0
External CE0 chip select. Active-low chip select for CE space 0.
EMIFCE1
External CE1 chip select. Active-low chip select for CE space 1.
EMIFCE2
External CE2 chip select. Active-low chip select for CE space 2.
EMIFCE3
External CE3 chip select. Active-low chip select for CE space 3.
EMIFBE[1:0]
Byte enables.
EMIFWAIT [1:0]
Used to insert wait states into the memory cycle.
EMIFWE
Write enable - active low during a write transfer strobe period
EMIFOE
Output enable-active low during the entire period of a read access.
EMIFRnW
Read-write enable
End of Table 2-1
EMIFD [15:0]
EMIFA [23:0]
EMIFCE [3:0]
EMIFBE [1:0]
External
Memory
EMIFWE
Interface
(EMIF16)
EMIFOE
EMIFWAIT [1:0]
EMIFRnW