4.5 Async 2 Config Register (A2CR)
SPRUGZ3A—May 2011
KeyStone Architecture External Memory Interface (EMIF16) User Guide
4-7
Chapter 4—Registers
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4.5 Async 2 Config Register (A2CR)
Bit fields and their operation are exactly the same as A1CR, except that programmed
values will be applied for CE1.
4.6 Async 3 Config Register (A3CR)
Bit fields and their operation are exactly the same as A1CR, except that programmed
values will be applied for CE2.
4.7 Async 4 Config Register (A4CR)
Bit fields and their operation are exactly the same as A1CR, except that programmed
values will be applied for CE3.
3-2
TA
0x3
Turn Around cycles.
Number of EMIF16 clock cycles between the end of one asynchronous memory access and the start
of another asynchronous memory access, minus one cycle.
This delay is not incurred between a read followed by a read, or a write followed by a write to the
same chip select. The reset value is 4 cycles.
1-0
ASIZE
Asynchronous Memory Size. Defines the width of the data bus.
0 – 8-bit data bus
1 – 16-bit data bus
2,3 – Reserved
End of Table 4-4
Table 4-4
Async 1 Config Register (A1CR) Details (Part 2 of 2)
Bit
Field
Reset Value
Description