Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 76 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 76 / 90
16h CLK-GEN 2 Command Byte 2 R/W 00h
17h CLK-GEN 2 Command Byte 3 R/W 00h
18h CLK-GEN 2 Read Data Byte 0 RO 00h
19h CLK-GEN 2 Read Data Byte 1 RO 00h
1Ah CLK-GEN 2 Read Data Byte 2 RO 00h
1Bh CLK-GEN 2 Read Data Byte 3 RO 00h
1Fh~2Ch Reserved 0s
3Fh~30h PM Bus (RFU) R/W 0s
50h
IDT5V41068 Clock Select Control
Register
R/W 0-h
Note :
“**” means the value may be changed in the future FPGA FW update release.
5.6.2 FPGA Configuration Registers Descriptions
Register Address: SPI Base + 00h
Register Name: FPGA Device ID (Low Byte) Register
Default Value:
04h
Attribute:
Read Only
Bit Description Read/Write
7-0
FPGA Device ID (Low Byte)
This offset 01h field combined with this field identifies the particular
device. This identifier is allocated by the FPGA design team.
RO
Register Address: SPI Base + 01h
Register Name: FPGA Device ID (High Byte) Register
Default Value:
80h
Attribute:
Read Only
Bit Description Read/Write
7-0
FPGA Device ID (High Byte)
This field combined with the offset 00h field identifies the particular
device. This identifier is allocated by the FPGA design team.
RO
Register Address: SPI Base + 02h
Register Name:
FPGA Revision ID (High Byte) Register
Default Value:
**
Attribute:
Read Only
Bit Description Read/Write
7-0
FPGA Revision ID (Low Byte)
This offset 03h register combined with this register specifies FPGA
device specific revision identifier. The value may be changed in future
FPGA FW update release.
RO