Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 69 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 69 / 90
5.3.3 Boot Configuration Timing
5.3.4 Boot Configuration Forced in I2C Boot
5.3.1 Power-On Sequence
The following section provides details of the FPGA Power-On sequence of operation.
1. After the EVM 3.3V auxiliary voltage (VCC3V3_AUX_PG) is valid and stable, and FPGA design code is
loaded, the FPGA is ready for the Power-On sequence of operation.
2. The FPGA starts to execute the Power-On sequence. Wait for 10 ms, the FPGA enable the 2.5V power.
3. Once the 2.5V voltages (VCC5_PG and VCC2V5_PG) are valid, wait for 5ms, FPGA asserts the
UCD9222_ENA1 and UCD9222_ENA2 to enable the CVDD and VCC1V0 DSP core power.
4. After UCD9222_PG1, UCD9222_PG2 and PGUCD9222 are all valid; FPGA waits for 5ms and then
enables 1.8V power.
5. After the 1.8V voltage is valid (VCC1V8_PG asserted), wait for 5ms and then:
a. Unlock the 1.8V outputs on the FPGA,
b. De-assert clock generator PD# pin; after driving PD# to high for 1ms, FPGA starts to initialize
clock generator.
6. After finishing the initiation of clock generator, FPGA waits and then enables 1.5V power rail.
7. Once the 1.5V voltage is valid (VCC1V5_PG), FPGA waits for 5ms and then enables 0.75V power and
Level shift component output and initializes the clock mux.
8. After 0.75V voltage is valid (VCC0V75_PG asserted), wait for 5ms and check the clock generator
PLL_LOCK states and FPGA asserts clock MUX OE pin, after the PLL state of clock generator is valid,
the
FPGA de-asserts DSP_RESETz and DSP_LRESETz and keeps DSP_PORz and
DSP_RESETFULLz in assertion.
9. After DSP_RESETz and DSP_LRESETz have been de-asserted, FPGA wait for 5ms and then de-
asserts DSP_PORz and keeps DSP_RESETFULLz still being asserted. Waits for another 5ms, then
FPGA de-asserts DSP_RESETFULLz. The FPGA will drive BM_GPIO switches value to DSP for the
DSP boot mode configuration strapping during the period from VCC0P75_PG is valid to the
RESETSTAT# being de-asserted. FPGA will also drive the PCIESSEN switch value to DSP_TIMI0 for
the DSP boot configuration strapping.
10. Wait for RESETSTAT# signal from DSP to go from low to high. The EVM Power-On sequence is
completed.
5.3.2 Power Off Sequence
Following section provides details of FPGA power off sequence of operation.
1. Once the system powers on, any power failure event (any one of power good signals de-asserted) will
trigger the FPGA to proceed to the power off sequence.
2. Once any de-asserted Power Good signals have been detected by FPGA, it will assert the DSP_PORz
and DSP_RESETFULLz to DSP immediately.
3. Wait for 5ms, FPGA will disable all the system power rails by the enable pins and clock generator by the
power down pin, assert all the other DSP resets to DSP, lock the +1.8V output pins from FPGA to DSP.
4. FPGA remains in the power failure state until main 12V power is removed and restored.