Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 72 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 72 / 90
almost everything. Soft Reset will behave like Hard Reset except that PCIe MMRs, EMIF16 MMRs, DDR3
EMIF MMRs, and External Memory contents are retained.
Boot configurations are not latched by Warm Reset. Also, Warm Reset will not reset blocks supporting Reset
Isolation when they are appropriately configured previously by application software. Warm Reset must be
used to wake from low-power sleep and hibernation modes.
In the case of a Soft Reset, the clock logic or the power control logic of the peripherals are not affected, and,
therefore, the enabled/disabled state of the peripherals is not affected. The following external memory
contents are maintained
During a Soft Reset:
o
DDR3 MMRs: The DDR3 Memory Controller registers are not reset. In addition, the DDR3 SDRAM
memory content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking
the soft reset.
o
PCIe MMRs: The contents of the memory connected to the EMIFA are retained. The EMIFA
registers are not reset.

COLD_RESET (RST_COLD1): Not used in current implementation.

MMC_POR_IN_AMC#: A logic low state with a low to high transition will trigger a Full Reset behavior
event.

MMC_WR_AMC#: A logic low state with a low to high transition will trigger a warm reset behavior event.

TRGRSTz: A logic low state with a low to high transition on the Target Reset signal from emulation
header that will trigger a warm reset behavior event.

FPGA_JTAG_RST#: Not used in current implementation.
5.5 SPI Protocol
This section describes the FPGA SPI bus protocol design specification for interfacing with TMS320C6657 DSP
and CDCE62005 clock generator. It contains:
5.5.1 FPGA DSP SPI Protocol
5.5.2 FPGA Clock Generator SPI Protocol
5.5.1 FPGA-DSP SPI Protocol
FPGA supports simple write and read commands for TMS320C6657 DSP to access the FPGA configuration
registers through SPI interface. The FPGA SPI bus clocks data in on the falling edge of DSP SPI Clock. Data
transitions therefore occur on the rising edge of the clock.
The figures below illustrate a DSP to FPGA SPI write operation.