Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 34 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 34 / 90
2.14 McBSP Interface
McBSP module provides a glueless interface to common telecom serial data streams. The number of active
serial links of McBSP0 and McBSP1 is four and they are connected to the AMC edge connector through a level
shift IC to support 3.3V I/O on the C6657 Lite EVM. The same signals are also provided on 80-pin Expansion
header without level translation (1.8V level). The selection between AMC connector and header is done by
McBSP_AMC_EN# signal. If this signal is low McBSP is accessed over AMC edge and FPGA provides the
required clocks and frame syncs. If this signal goes high, these clocks and syncs are tri-stated and McBSP is
accessed over 80-pin header. For more information, see the
McBSP User Guide for the C6657 DSP .
The figure below shows McBSP connectivity to AMC backplane and 80-pin header on EVM.
DSP
(C6657)
McBSP Data
McBSP Clks
FPGA
(XC3S200AN)
LVL TXL
(SN74AVC4T245)
80-pin Expansion
Header
EN#
4
4
8 10
10
4
TCLK[D:A]
AMC
CON
Port 12
(3.3V)
(1.8V)
Figure 2.12: C6657 Lite EVM McBSP Interface
The figure below shows the McBSP clock generation by the FPGA and the table below explains the TCLK
selection for McBSP Clock and frame sync generation.
FPGA
XC3S200AN
TCLKA+/-
TCLKB+/-
(Through NU Caps)
TCLKC+/-
TCLKD+/-
McBSP_SCLK_[1:0]
McBSP_RxCLK_[1:0]
McBSP_TxCLK_[1:0]
McBSP_FSR_[1:0]
McBSP_FST_[1:0]
A
M
C
C
O
N
DSP
(C6657)
Figure 2.13: C6657 Lite EVM McBSP Clock Generation by FPGA