Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 59 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 59 / 90
4.2.3 VCC5 Design
TPS54321
C = 22uF x 1
10uF x 1
VCC5
L = 22uH
Figure 4.6: VCC5 Power Design on C6657 Lite EVM
Over all tolerance 5%,
DC tolerance is 2.5%
K
IND
= 0.3
Output Capacitor Calculation Inductor Calculation
C
out(min)
= 1 / (2
π*(V
o
/I
o
)*F
co(max)
)
= 1/( 2 * 3.14 * (5/0.8)* 570kHz)
≈ 44.7nF
L = ((V
in(max)
- V
out
)/(I
out
* K
ind
)) * (V
out
/(V
in(max)
* F
sw
))
= ((12.5 - 5)/(0.8 * 0.3) * (5 / (12.5 * 570kHz))
= (7.5/0.24) * (5 / (7.125M))
= (31.25) * (0.7M)
≈ 21.87uH
Reference Capacitor = 22uF + 10uF
Reference Inductor = 22uH
The
VCC5
power rail is regulated by TI 2A Step Down SWIFT™ DC/DC Converter, TPS54231, to supply the
power of the XDS560v2 Mezzanine Card on C6657 Lite EVM.
4.3 Power Supply Boot Sequence
Specific power supply and clock timing sequences are identified below. The TMS320C6657 DSP requires
specific power up and power down sequencing. Figure 4.2 and Figure 4.3 illustrate the proper boot up and down
sequence. Table 4.3 provides specific timing details for Figure 4.6 and Figure 4.7.
Refer to
TMS320C6657 Data Manual for confirmation of specific sequencing and timing requirements.
Table 4.2: Power-up and down timing on C6657 Lite EVM
Step Power Rails Timing Description
Power-Up
1
VCC12 (AMC Payload power),
VCC3V3_AUX,
VCC1V8_AUX
VCC1V2
Auto
When 12V power is supplied to C6657
Lite EVM then 3.3V, 1.8V and 1.2V
supplies to FPGA will turn on. FPGA
outputs to DSP will be locked (held at
ground).
2 VCC5,VCC2V5 10ms
Turn on VCC5 and VCC2V5 after
VCC3V3 is stable for 10ms.
3 CVDD (DSP AVS core power) 5ms
Enable CVDD (UCD9222 power rail#1)
after both of VCC5 and VCC2V5 are
stable for 5ms.
4
VCC1V0 (DSP CVDD1 fixed core
power)
5ms
Enable VCC1V0 (UCD222 power rail#2)
5ms after CVDD has stabilized. The start-