Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 22 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 22 / 90
2.2 EVM Boot mode and Boot Configuration Switch Settings
C6657 Lite EVM has three configuration switches SW3, SW5 and SW9 that contain 18 values latched when reset
is released. This occurs when power is applied the board, after the user presses the FULL_RESET push button
or after a POR reset is requested from the MMC.
SW3, SW5 and SW9 determine general DSP configuration, Little or Big Endian mode and boot device selection,
DSP boot device configuration, CorePac PLL setting and PCIe mode selection and enable.
Please refer to
Section 3.3 of this document for default switch setting and details of each switch. For more
information on DSP supported Bootmode, refer TMS320C6657 Datasheet and C66x Boot Loader User Guide.
Table 2.2: Boot Configuration Selection
DIP Switch DSP GPIO/ BM Primary Function Selection
SW3 (Pin 1) ENDIANESS ENDIANESS
0 - Big Endian
1 - Little Endian
SW3 (Pins [5:2]) BOOTMODE[3:0] BOOTMODE Device
0000 - Sleep/EMIF16
0001 - SRIO
X010 - Ethernet
0011 - NAND
0100 - PCIe
X101 - I2C Master
0101 - I2C Slave
X110 - SPI
0111 - HyperLink
1000 - UART
SW3 (Pins [6:8])
SW5 (Pins [1:3])
BOOTMODE[9:4] Boot Device Configuration Depends on Boot Mode Selection
SW5 (Pins [6:4]) BOOTMODE[12:10]
PLL Multiplier/I2C (Input Clock
Frequency)
000 - 50.00 MHz
001 - 66.67 MHz
010 - 80.00 MHz
011 - 100.00 MHz
100 - 156.25 MHz
101 - 250.00 MHz
110 - 312.50 MHz
111 - 122.88 MHz
SW5 (Pins [8:7]) PCIESSMODE[1:0] Endpt/RootComplex
00 - End-point mode
01 - Legacy End-point mode
(support for legacy INTx)
10 - Root complex mode
11 - Reserved
SW9 (Pin 1) PCIESSEN PCIESSEN
0 - PCIe module disabled
1 - PCIe module enabled