Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 74 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 74 / 90
Figure 5.6: SPI access from TMS320C6657 to FPGA (READ)
5.5.2 FPGA- CDCE62005 (Clock Generator) SPI Protocol
The FPGA-Clock Generator SPI interface protocol is compatible to CDCE62005 SPI. The FPGA SPI bus clocks
data in on the rising edge of DSP SPI Clock. Data transitions therefore occur on the falling edge of the clock.
The figure below illustrates a FPGA to CDCD62005 SPI write operation.
Figure 5.7: SPI access from FPGA to CDCE62005 (WRITE)
The figure below illustrates a FPGA to CDCD62005 SPI read operation.
Figure 5.8: SPI access from FPGA to CDCE62005 (READ)