Technical Reference Manual
TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 67 / 90
DSP_LRESETNMIENZ
O
Latch Enable for DSP Local Reset and NMI
inputs:
The default value is 1b and a register bit
defines the state of this pin.
DSP_NMIZ
O
DSP NMI:
The default value is 1b and unlocked a
register bit defines the state of this pin.
DSP_LRESETZ
O
DSP Local Reset:
The default value is 1b and a
register bit defines the state of this pin.
DSP_HOUT
I
DSP HOUT
DSP_BOOTCOMPLETE
I
DSP Boot Complete Indication
DSP_SYSCLKOUT
I
DSP System Clock Output
DSP_PORZ
O
DSP Power-On Reset
DSP_RESETFULLZ
O
DSP Full Reset
DSP_RESETZ
O
DSP Reset
FPGA Storage (RFU):
FPGA_SPI_CS#
O
FPGA SPI Chip Select:
(RFU)
FPGA_SPI_SI
O
FPGA SPI Serial Data MOSI:
(RFU)
FPGA_SPI_SCK
O
FPGA SPI Clock Output:
(RFU)
FPGA_SPI_SO
I
FPGA SPI Serial Data MISO:
(RFU)
DSP TDM CLK :
DSP_TSIP0_FS[A:B]0
DSP TSIP0_FS[A:B]0:
The single-ended clock
(DSP_TSIP0_FSA0 and DSP_TSIP0_FSB0) outputs
are derived from the differential TDM Frame
Synchronization (TDM_CLKC) input.
DSP_TSIP1_FS[A:B]1
DSP TSIP1_FS[A:B]1:
The single-ended clock
(DSP_TSIP1_FSA1 and DSP_TSIP1_FSB1) outputs
are derived from the differential TDM Frame
Synchronization (TDM_CLKC) input.
DSP_TSIP0_CLK[A:B]0
DSP TSIP0_CLK[A:B]0:
The single-ended clock
(DSP_TSIP0_CLKA0
and
DSP_TSIP0_CLKB0)
outputs are derived from the differential TDM clock
(TDM_CLKA) input.
DSP_TSIP1_CLK[A:B]1
DSP TSIP1_CLK[A:B]1:
The single-ended clock
(DSP_TSIP1_CLKA1
and
DSP_TSIP1_CLKB1)
outputs are derived from the differential TDM clock
(TDM_CLKA) input.
TDM_CLKA[p/n]
I, Diff
TDM_CLKA Different Clock Input Pairs:
The
reference clock referring to TSIP0/1 CLKs of DSP.
TDM_CLKB[p/n]
(RFU)
I, Diff
TDM_CLKA Different Clock Input Pairs:
The
reference clock referring to TSIP0/1 CLKs of DSP.
TDM_CLKC[p/n]
I, Diff
TDM_CLKA Different Clock Input Pairs:
The
reference clock referring to TSIP0/1 CLKs of DSP.
TDM_CLKD[p/n]
(RFU)
I, Diff
TDM_CLKA Different Clock Input Pairs:
The
reference clock referring to TSIP0/1 CLKs of DSP.
DEBUG LED:
DEBUG_LED[1:4]
O
Debug LED:
These LEDs are used for debugging
purpose only. Can be configured by the FPGA
registers
Miscellaneous:
MAIN_48MHZ_CLK_R
I
FPGA Main Clock Source:
A 48 MHz clock is used
as the FPGA main clock source.
Summary of Contents for eInfochips TMDXEVM6657L
Page 19: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 19 90...
Page 20: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 20 90...
Page 21: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 21 90...
Page 77: ...Technical Reference Manual TMDXEVM6657L SPRUHG7 Revised August 2012 TMDXEVM6657LE Page 77 90...