Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 33 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 33 / 90
2.12 HyperLink Interface
TMS320C6657 provides HyperLink bus for companion chip/die interfaces. This is a four lane SerDes interface
designed to operate at 12.5 Gbps per lane and is used to connect with external accelerators.
The interface includes the Serial Station Management Interfaces used to send power management and
flow messages between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as
two 2-wire output buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.
For more information, see
Hyperlink Interface for KeyStone Devices User Guide .
The figure below shows Hyperlink bus connections on the C6657 Lite EVM.
RX[3:0]
DSP
(C6657)
HyperLink CON
(IPASS + HD)
Tx Port x 4
Rx Port x 4
PM
FL
TX[3:0]
PM
FL
HYPERLINK_CLK
250MHz
(LVDS)
Figure 2.10: C6657 Lite EVM HyperLink Interface
2.13 PCIe Interface
The 2 lane PCI express (PCIe) interface on C6657 Lite EVM provides a connection between the DSP and AMC
edge connector. The PCI Express interface provides low pin count, high reliability, and high-speed data transfer
at rates of 5.0 Gbps per lane on the serial links. For more information, see the
Peripheral Component
Interconnect Express (PCIe) for KeyStone Devices User Guide .
The figure below shows the PCIe connectivity to AMC backplane on EVM.
Figure 2.11: C6657 Lite EVM PCIe Interface