Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 27 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 27 / 90
2.5 Clock Domains
The EVM incorporates variety of clocks to the TMS320C6657 as well as other devices which are configured
automatically during the power up configuration sequence. The figure below illustrates the clocking for the system
in EVM module.
88E1112
MSP430
XTAL
25MHz
XTAL
32.768kHz
C6657
CDCE62005
U0
U1
U2
U3
U4
250.0 MHz
250.0 MHz
PRI REF
50.0 MHz
100.0 MHz
XTAL
25MHz
DDR_CLKP/N
CORE_CLKP/N
SRIO_SGMII_CLKP/N
HYPERLINK_CLKP/N
100.0 MHz
PCIe_CLKP/N (from AMC)
PCIe_CLKP/N
FT2232HL
XC3S200AN
XTAL
12MHz
Osc
48MHz
Mux
100 MHz
XC3S200AN
2
McBCP_Rx_CLK
McBCP_Tx_CLK
McBCP_SL_CLK
McBCP_FSR
McBCP_FST
2
2
2
2
TCLKA+/-
(from AMC)
TCLKB +/-
(NU, from AMC)
TCLKC +/-
(from AMC)
TCLKD +/-
(from AMC)
TCLKB +/-
TEST HDR
(80pins)
McBCP_Rx_CLK
McBCP_Tx_CLK
McBCP_SL_CLK
McBCP_FSR
McBCP_FST
A
M
C
C
O
N
Figure 2.3: C6657 Lite EVM Clock Domains
Table 2.5: Clock Configuration
Clock Frequency Description
CORECLKP/N 100.00MHz Core Clock Input for DSP (Differential)
DDRCLKP/N 50.00MHz DDR3 Clock Input for DSP (Differential)
DSP_PCIECLKP/N 100.00MHz PCIe Clock Input for DSP (Differential)
HyperLink_CLKP/N 250.00MHz Hyperlink Clock Input for DSP (Differential)
SRIOSGMIICLKP/N 250.00MHz SRIO SGMII Clock Input for DSP (Differential)
TCLKAP/N 16.384MHz Clock Input for McBSP Interface (Differential)
TCLKBP/N 25.00MHz Clock Reference for CLK1(Differential)
TCLKCP/N 8.00KHz Frame Sync Input for McBSP Interface (Differential)
TCLKDP/N TBD RFU (Differentail)