Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 70 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 70 / 90
5.3.3 Boot Configuration Timing
The boot configuration timing of the power-up and the RESETFULLz event are shown below.
VCC0V75_PG
RESETz
RESETFULLz
RESETSTATz
PORz
T=5ms
T=5ms
CLOCK2_PLL_LOCK
T=5ms
All 0 Boot Config Switches value driven by FPGA
Floating by FPGA
DSP GPIOs
T=3~4 48MHz
clock cycle
Figure 5.1: Power-On Reset Boot Configuration Timing
RESETFULLzSW
RESETFULLz
RESETSTATz
T=5ms
Boot Config Switches value driven by FPGA Floating by FPGA
Floating by FPGA
DSP GPIOs
T=4 samples
(0.5ms clock)
T=4 samples
(0.5ms clock)
T=3~4 48MHz
clock cycle
Debounce ckt
Debounce ckt
Figure 5.2: Reset-Full Switch/Trigger Boot Configuration Timing