Tektronix WFM601, Service Manual

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Theory of Operation
WFM 601 - Service Manual
3–21
The Data Buffers, U15 and U19, are bidirectional. When the DIR control line is
low data from the NOVRAM, RAM, and FLASH EPROM is read into the
Microprocessor data bus on the DATA EN2. When DIR is pulled high, and
DATA EN2 is pulled down (by the Decoder), the Microprocessor writes to the
Data Buffers on the data bus.
The NOVRAM (U14) stores all of the constants used by the Microprocessor.
The Microprocessor writes the 8 MSBs into the NOVRAM when both CE and
WE are pulled low. RW from the Microprocessor pulls down WE. CE is pulled
low by NOVRAM which is decoded by the address decoder. Content of the
NOVRAM is read back out to the Microprocessor, through the Data Buffer
(U19), when RW goes high and the CE and OE are pulled low by NOVRAM.
System level code is loaded into RAM (for reading by the Microprocessor) from
the Flash EPROM, where it is stored. Unless VPP is high (for programming
purposes) the Flash EPROM, U10 & U16, functions as a 256k X 8 Read Only
Memory (ROM). (Write instructions are ignored.) U10 stores the lower 8 bits
and U16 the upper 8 bits. It is read out when FLASH, RD LO, and RD HI are
pulled low.
Flash EPROM output is written into the Random Access Memory (RAM), U11
& U17, when SRAM, WR LO, and WR HI are pulled low. The Microprocessor
reads the RAM when SRAM, RD LO, and RD HI are pulled low.
The Address Decoder is U21. It is a 3-line to 8-line decoder using the three
MSBs of the address bus to output five control signals. The decoder is enabled
when the Microprocessor pulls DECODE and ADDR EN low.
U2 is a logic array that decodes Microprocessor outputs. It uses buffered address
0 (BA0) as a clock. Its outputs enable the data and address buffers, control read
and write for the RAM and Flash EPROM, and output two control signals for
digital expansion.
U23 buffers five outputs and one input for the Microprocessor. It is permanently
enabled by tying pin 1G low and pulling pin 2G low.
Diagram 15 Dynamic Control
Microprocessor instructions are synchronized to line and field rates to generate
time-dependent control signals by the circuitry on this diagram.
The sync separator consists of U68 and U71. The V sync and H sync outputs are
used to synchronize the Line Rate Controller (U34). The two integrated circuits
NOVRAM, RAM, & Flash
EPROM
Decoders
Buffered Output
Sync Separator