Tektronix WFM601, Service Manual

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Theory of Operation
3–2
WFM 601 - Service Manual
Block Diagram 1
Input and Waveform Monitor
This block diagram contains the serial inputs, outputs, and the vertical and
horizontal amplifiers along with the crt and blanking.
The component serial digital video signal is input through buffered, 75W
compensated bridging loop-through circuits. After equalization, deserializing,
and descrambling, the signal is input to a Coprocessor. The equalized serial
component signal is also re-clocked to provide a serial video signal output to
drive other equipment.
Input signal is selected by front-panel Serial A, Serial B selection switch. Only
one input at a time may be displayed.
The Coprocessor, which has parallel digital (deserialized) video as an input,
generates signals used to display the video signal on the WFM
601 CRT and
provide transcoded analog outputs. The Coprocessor outputs a word synchroniz-
ing pulse to enable the recovery of the R–Y and B–Y channels from the
multiplexed video data stream. In addition, it generates the signals used to
clamp, re-establish the vertical blanking interval, and provide composite
synchronization. The Coprocessor also removes nonvideo data from the signal,
which includes End of Active Video (EAV), Start of Active Video (SAV) and
ancillary data. Lastly the Coprocessor maintains a handshake with the Micropro-
cessor over the Microprocessor data bus.
The multiplexed video data stream from the Coprocessor is converted to analog
components by three Digital to Analog Converters. Video data is delayed prior
to application to the Y channel Half-Band Filter. Enable signals (Timing) for the
Y Delay and the two color difference Half-Band Filters are generated by the
Coprocessor.
The Half-Band Filters are clocked at twice the timing signal frequency by a
signal that is equal to or counted down from the 27 MHz clocking signal. The
clock signals are generated by the Phase-Locked Loop. Timing (enable) signals
are 13.5 MHz for luminance and 6.75 MHz for color difference. Clocking
signals are at 2X the timing signal. The half-band filtered digital component
signals are input to three DACs that are clocked at 2X the timing frequency
(Y=27 MHz, P
B
and P
R
=13.5 MHz.) The DAC outputs are the component
analog signals (Y, P
B
, P
R
), whose gain is Microprocessor controlled through the
DACs.
Serial Input/Output
Coprocessor
Y Delay, Half-Band Filters,
and Digital to Analog
Converters (DAC)s