Tektronix WFM601, Service Manual

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Theory of Operation
3–20
WFM 601 - Service Manual
signal. U47D is an inverter to generate the –H RO SIG. Output is controlled by
the H RO SEL signal from the Line Rate Controller.
Horizontal levels, such as Gain and Position from the DACs (Diagram 17), and
control signals, such as Mag from the Line Rate Controller (Diagram 15), are
input through U56, the Horizontal Amplifier. Gain and frequency response
characteristics of the CRT are compensated for by a network between the
VOUT+ and VOUT– terminals. The + and –H signals from the VOUT terminals
are also supplied to the Vertical Deflection Amplifier (Diagram 6) for ortho-
gonality adjustment (Y-Align).
The Horizontal Deflection circuit consists of seven discrete transistors to drive
the horizontal deflection plates of the CRT with a differential signal.
Q28 is the current source for this paraphrase amplifier. The amplifier itself is
driven from inputs Q12 and Q14. Their bases are a summing junction for the
input signal and compensated feedback. Q11 and Q13 are common base
amplifiers with the bases held at –3 V. Q8 and Q15 are driven independently.
Shunting resistors across Q8 and Q15 lessen power dissipation in the current
source (Q28).
CR8 is a boot strap circuit to divert current to the negative-going side when the
amplifier is slewing rapidly.
Diagram 14 Microprocessor
The Microprocessor controls the functions of the WFM 601. It has a 32-bit
internal architecture and operates with a 16-bit data bus and a 24-bit address bus.
U18 is the Microprocessor. It is crystal controlled, with Y1 as the active element
of the clock oscillator. DS1 is an indicator that turns on and holds when the 5V
supply stabilizes during turn on. U7 senses the 5V supply and pulls the RESET
line low if the 5V supply goes low.
LS1 is a permanent magnet-type speaker for audible feedback that is driven by
Q3. CR2 is an inductive compensation for the speaker voice coil.
U13 is a Read Only Memory (ROM) with 18 addresses; it outputs the 8 Most
Significant Bits (MSB) to the data bus.
U5, U8, and U12 are the address buffers for the 24-bit address bus. The bus is
enabled by ADDR EN2 from the decoder. The DIR control line is held high
allowing the processor to write to the buffer whenever the ADDR EN2 is pulled
down. The buffered address bus selects addresses in the NOVRAM, RAM, and
FLASH EPROM.
Horizontal Deflection
Microprocessor & ROM
Data and Address Buffers