Tektronix WFM601, Service Manual

Page: 67 / 304

Theory of Operation
3–10
WFM 601 - Service Manual
Diagram 4 Clocks, Power, & Interconnects
U16 is a TTL to ECL converter whose noninverting output drives one input of
an exclusive OR gate that serves as a phase detector to compare the regenerated
clock to the input clock signal. The output of U24C drives an operational
amplifier that serves as the error amplifier. U14A is compensated by a feedback
circuit that sets the phase lock loop bandwidth. The placement of P1 dictates the
bandwidth, which determines the speed of lockup. The output of U14A is the
error signal that drives CR7, a varactor diode in the oscillator circuit.
U24A is an exclusive OR gate wired as a crystal controlled (Y1) 13.5 MHz
oscillator. Its output is phase shifted, with one phase delayed, and applied to an
exclusive OR gate, U24B to output a 27 MHz signal. The inverted output of
U24B is fed back to one input of the phase detector to determine if the oscillator
output and the incoming clock are in phase. The Side Band Filter cleans up the
Frequency Doubler output prior to conversion back to TTL.
U27 is a differential ECL to TTL converter that outputs 27 MHz clocking signals
for the Luminance Half-Band Filter and Digital-to-Analog Converter (DAC).
U93 is a Programmable Logic Array (PAL) that generates the 13.5 and 6.75
MHz enable and clock signals for the recovery of the luminance and color
difference signals from the digital input. Because the Y P
B
and P
R
signals are
present on the digital signal at different times it is necessary to clock the
half-band filters at the correct times to convert the digital signal into the analog
components. The Y Time signal, that enables the divided down outputs, is
generated by the Coprocessor on Diagram 3. The clocking signal, to be divided
down, is the 27 MHz regenerated clock.
The –5.2V supply is a continuous mode flyback switching supply that uses the
instr40V supply as a power source. The switch is Q1, a field-effect
transistor (FET), running at a 100 kHz rate. Its duty cycle sets the output
voltage. U23 is the controller whose switching rate is set by C42 and R88,
connected to pin 4. The +5V supply, at pin 8, is the reference for the controller.
C51 and R90 (pin 1) are the compensation for the controller internal error
amplifier.
U22A is the voltage feedback amplifier for the controller. It is an inverting
operational amplifier with a gain of –0.5. During normal operation its output is
+2.5V, which is the voltage required by the controller.
CR101 and C171 limit any voltage spikes at the drain of Q1 to 100V. The
snubber circuit is composed of C1, CR3, and the parallel network of R90, R91,
Phase Detector and Error
Amplifier
OSC, Frequency Doubler,
and Sideband Filter
ECL to TTL Conversion
Clock PAL
–5.2 Supply