Tektronix DM 5010, Instruction Manual

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Theory of Operation —DM 5010
Initially, pin 3 of U1635B is high. As the 250 kHz clock is
applied to U1730, counting begins. When U1730's binary
outputs equal 7, a high is applied to the J input of U1320B
via U1635C and U1530B. The falling edge of the 250 kHz
clock (actually rising Q) clocks the high to the Q output (T8)
of the U1320B. The complementary low at its Q output is
applied to U1635B and disables the next clock to U1730.
The J input of U1320B is high (U1730’s count is still 7) and
the K input is latched high by the Q output. The T8 interval
line at the Q output of U1320B is toggled low by the next
250 kHz clock, re-enabling the clock to U1730 (Q goes
high). Once again U1730 counts normally until its binary out­
put equals 15. On the falling edge of the 250 kHz clock, a
high is clocked to the Q output of U1320B and the comple­
mentary low at its Q output disables the next clock through
U1635B.
Line T16 at pin 15 of U1730 goes high when its binary
output equals 15 (actually count 16 because one clock is
skipped). The next clock (17th) sets the T17 output at pin 5
of U1630A high and, on its falling edge, clocks to LU 730 are
re-enabled. The rising edge of the next 250 kHz clock sets
the binary outputs of U1730 back to zero and inflates the TO
pulse at the terminal of flip-flop U1630B. Although genera­
tion of a TO pulse is actually dependent on the presence of a
T17 pulse, the instrument considers T17 to be the last pulse
of the sequence and TO to be the beginning of the next
sequence.
Integrated circuit U1525 is a negative-edge-triggered bi­
nary counter that counts the number of 18-count charge­
balancing intervals completed. As U1525 requires a
negative clock, T17 is applied to its clock input to signal the
end of an 18-count interval.
The NAND gates connected to the binary outputs of
U1525 generate two time-dependent control signals re­
quired by the Control Logic to perform an A/D conversion.
During normal 4 1/2 digit operation, U1520C detects when
1536 measure intervals have occurred during the Auto-Zero
period and causes a high EOAZ (End Of Auto-Zero) at pin 3
of U1520A, signalling that the Auto-Zero process should
stop. At this time, the zero-reference voltage in the charge­
balancing converter stage has been set. The counter is
reset by CLR1 and the actual A/D measurement begins.
A measurement requiring 4 1/2 digit acuracy requires
that the integrator integrate over 12 or 10 periods of the
power line frequency for 60 or 50 Hz operation, respectively.
Referring to Fig. 4-13,
it can be seen that any noise at the
instruments input affects the charge and discharge rates at
the A/D Converters summing node (and thus the time at
which the node voltage crosses the zero-reference voltage).
In the DM 5010’s charge-balancing A/D conversion, the
time (number of counts) that the Integrators output voltage
is above the zero-reference voltage is subtracted from the
time below the zero-reference voltage, and is representative
of the input voltage. Though the magnitude of the ripple and
the charge rates are extremely exaggerated in Fig. 4-13. a
principle may be demonstrated.
If, for example, a measurement is taken over time inter­
val A, the noise (at power line frequency) added to the sum­
ming node of the “antenna effect" of the test leads, results
in a conversion more positive than the actual signal being
measured. Similarly, a measurement taken over time inter­
val B results in a conversion more negative than the actual
signal.
By making the A/D conversion over a complete number
of power-line cycles (A + B), these measurement errors
cancel and the actual signal is accurately resolved. Since
the DM5010 will be used in environments where either
50 Hz or 60 Hz power is in use, the chosen time frame re­
sults in “complete-cycle ” measurements for either line
frequency.
For normal 4 1/2 digit measurements, U1620 detects
when 2778 measurement intervals have occurred. This is
equivalent to 200.02 ms of time or, in terms of “complete
cycles', 12 cycles at 60 Hz or 10 cycles at 50 Hz. After the
instrument measures for 200.02 ms, U1620 applies a low at
U1635A, generating an EOC (End Of Count) pulse at its
output. This EOC signals the Control Logic stage that the
Measure Period of the measurement is over.
The DM 5010 also has the capability to perform 3 1/2
digit measurements at a faster rate. If the microprocessor
determines that a 3 1/2 digit measurement should be initiat­
ed,
it sets the 3 1/2 line high. This enables U1520B to gener­
ate the EOAZ pulse after 256 measure intervals have
occurred during Auto-Zero. Integrated circuit U1525 is reset
and begins to count measurement intervals for a 3 1/2 digit
conversion.
Once again, because of the power-line noise picked up
by the measurement leads, the A/D conversion must be per­
formed over a number of complete power-line cycles. Ade­
quate resolution for a 3 1/2 digit measurement may be
obtained by performing the A/D conversion over just one
power-line cycle at either 50 Hz or 60 Hz. Both U1625 and
U1720 are enabled by the high 3 1/2 line and, if operating
from a 60 Hz power line, the 50/60 mode-select-enable to
U1720 is also high (this is set by an internal jumper to match
the power-line frequency).
ADD JAN 1982
4-19