Tektronix DM 5010, Instruction Manual

Page: 75 / 347

Section 4— DM 5010
THEORY OF OPERATION
BLOCK DIAGRAM DESCRIPTION
This discussion is provided to aid in understanding the over­
all concept of the DM5010 Programmable Digital
Multimeter. The basic block diagram of the DM 5010 in Sec­
tion 10, Diagrams and Circuit Board Illustrations, should be
followed when reading the Block Description.
General Description
The DM5010 Programmable Digital Multimeter is a
microprocessor based GPIB programmable instrument de­
signed to
operate in any two adjacent compartments of a
TM 5000-Series power module. It has dual-polarity floating­
voltage measurement capabilities as well as the ability to
offset or null resistance and voltage measurements under
user control. It uses a charge balancing technique to convert
the analog input signals to digital data for storage and
processing.
To understand how the DM 5010 functions, some con­
cepts and techniques implemented in the instrument are ex­
plained at this point. These concepts should be understood
before proceeding to the block diagram and detailed circuit
descriptions in this section.
Isolation
The floating measurement capability allows the DM 5010
to accurately measure voltages referenced to a point other
than DMM chassis ground. To accomplish this, the
DM 5010 implements an isolation scheme. The TM 5000
power module supplies power to the analog and isolated
sections through a transformer to electriclaly isolate it from
the chassis ground. The required data and control signals
to/from this section are transmitted via opto-isolators, com­
pleting the isolation scheme. Isolating the “front-end",
where the critical portion of the measurement process oc­
curs, from chassis ground eliminates many problems inher­
ent in ground-related measurement techniques.
Charge Balancing
The DM 5010 Programmable Digital Multimeter operates
on the principle that each of its various measurement modes
(de volts, ac volts, Ohms, etc.) may, through proper input
conditioning, be translated into a de voltage representing
the conditions present at the instruments inputs. After input
conditioning, four major tasks remain:
1. conversion of the representative voltage to a digital
form that may be stored and manipulated as necessary;
2. keeping track of measurement specifics (i.e., type,
range, etc.);
3. performing any secondary conditioning or algorithms
dependent on 2, above, and;
4. presenting the resultant measurement data to the
user in a visible display or, if desired, to another device in
some intelligent format.
The latter three functions are performed and controlled
mostly by microprocessor and GPIB circuitry and are de­
scribed more fully later in this section. In this instrument, the
conversion of step 1 is performed using the charge-balanc­
ing A/D conversion technique.
Charge balancing conversion operates on the following
principle. An unknown (voltage-dependent) current lin inject­
ed into
an integrator’s input causes the integrator’ s output
to charge away from its initial value at some unknown rate.
Similarly, either injecting or removing a known net current
Inet ref in or I net ref out at the input node causes the integrators
output to integrate down and up, respectively, at a known
rate. If the unknown current and one of the known net cur­
rents (either injected or removed) are applied to the node
simultaneously, the integrators output charges at a rate de­
termined by the sum of the currents. If the reference cur­
rents Inet ref in and lnet ref out are chosen to always be
greater in magnitude than any allowed value of \jn, the inte­
grators output charges in the direction established by the
reference current switched into the summing mode. Charge
rate is established by + l/h -
A conversion is accomplished by keeping track of the
time required in each of its I net ref + Iin charge modes to keep
the integrators output near a predetermined zero-reference
voltage. By attaching a comparator to the zero-reference
voltage and to the output of the integrator, it may be deter­
mined whether the integrators output is above or below the
zero-reference. By adding or subtracting clock pulses to a
counter in response to the comparator output, a numerical
representation of the net time required by I net ref to balance
the effect of Iin on the integrator capacitor is generated. The
system microprocessor translates the numerical results into
a meaningful data format for display to the user.
REV JAN 1982
4-1