TechNexion PICO-IMX6, Hardware Manual

Page: 55 / 64

PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page 55 of 64
PIN
CPU
BALL
CPU PAD NAME Signal V I/O Description
X2_60 GND P Ground
X2_61 H3 DSI_CLK0M DSI_CLK0M 2V5 O
MIPI Display Serial Interface
clock pair negative signal
X2_62 B3 PCIE_TXP PCIEA_TXP 2V5 O
PCI Express Transmit output
differential pair positive
signal
X2_63 H4 DSI_CLK0P DSI_CLK0P 2V5 O
MIPI Display Serial Interface
clock pair positive signal
X2_64 A3 PCIE_TXM PCIEA_TXN 2V5 O
PCI Express Transmit output
differential pair negative
signal
X2_65 R5 GPIO_8 GPIO_8 3V3 I/O
General Purpose Input
Output
X2_66 GND P Ground
X2_67 T3 GPIO_6 GPIO_6 3V3 I/O
General Purpose Input
Output
X2_68 B2 PCIE_RXP PCIEA_RXP 2V5 I
PCI Express Receive input
differential pair positive
signal
X2_69 R7 GPIO_3 GPIO3_CLKO 3V3 I/O
General Purpose Input
Output
X2_70 B1 PCIE_RXM PCIEA_RXN 2V5 I
PCI Express Receive input
differential pair negative
signal