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PICO-IMX6 REV. A1. HARDWARE MANUAL

– VER 1.01 – JAN 28 2016

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64

Figure 7 - PICO-IMX6-EMMC Bottom view

Item

Description

Item

Description

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Memory IC

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eMMC Storage IC

3

Intel® Edison Compatible Connector

4

Expansion Connector 1

5

Expansion Connector 2

1

3

2

5

4

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Summary of Contents for PICO-IMX6

Page 1: ...PICO IMX6 REV A1 VER 1 01 January 28 2016...

Page 2: ...L VER 1 01 JAN 28 2016 Page 2 of 64 REVISION HISTORY Revision Date Originator Notes 1 00 September 30 2015 TechNexion Initial Public release 1 01 January 28 2016 TechNexion Minor changes and updated r...

Page 3: ...torage PICO IMX6 EMMC Only 21 2 3 1 Sandisk iNAND SDIN7DP2 21 2 3 2 Kingston KE4CN2H5A 22 2 3 3 Micro SD Cardslot PICO IMX6 SD only 23 2 5 Broadcom BCM4339 WiFi Bluetooth SiP Module 24 3 PICO Compute...

Page 4: ...d Accessories 56 5 1 PICO IMX6 Evaluation Kits 56 5 1 1 PICO Evaluation Start Kit Pack Content 56 5 2 PICO Compatible Displays 57 5 2 1 LVDSEXPANDER Translation Board to Connect to LVDS Panels 57 5 2...

Page 5: ...ignal Description 33 Table 12 I2S Audio Signal Description 34 Table 13 PCI Express Signal Description 35 Table 14 Serial ATA Signal Description 36 Table 15 USB Host Signal Description 37 Table 16 USB...

Page 6: ...ty Chart 11 Figure 4 PICO IMX6 Dimensional Drawing 12 Figure 5 PICO IMX6 Top view 13 Figure 6 PICO IMX6 SD Bottom view 13 Figure 7 PICO IMX6 EMMC Bottom view 14 Figure 8 NXP i MX6 Processor Blocks 15...

Page 7: ...an ideal building block that easily integrates with a wide range of target markets requiring rich multimedia functionality powerful graphics and video capabilities as well as high processing power com...

Page 8: ...on Unauthorized modifications or attachments could damage the device and may violate regulations governing radio devices These suggestions apply equally to your device battery charger or any enhanceme...

Page 9: ...encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect th...

Page 10: ...PICO IMX6 REV A1 HARDWARE MANUAL VER 1 01 JAN 28 2016 Page 10 of 64 1 3 Block Diagram Figure 1 PICO IMX6 SD Block Diagram Figure 2 PICO IMX6 EMMC Block Diagram...

Page 11: ...Ethernet Signaling LVDS 1 single channel 18 24 bit HDMI 1 HDMI ver 1 4 compatible TTL Display 1 TTL 18 24 bit Display PCIe 1 Lane PCIe 2 0 SATA Not available Check PICO IMX6POP for availability USB Ho...

Page 12: ...ensional Drawing The PICO IMX6 Compute Module is partly size compatible with Intel Edison and adds several additional I O expansion interfaces on an enlarged footprint 2D and 3D files can be obtained...

Page 13: ...ew Item Description Item Description 1 NXP i MX6 Processor 2 Memory IC 3 BCM4339 WiFi Bluetooth IC 4 Antenna connector Figure 6 PICO IMX6 SD Bottom view Item Description Item Description 1 Memory IC 2...

Page 14: ...L VER 1 01 JAN 28 2016 Page 14 of 64 Figure 7 PICO IMX6 EMMC Bottom view Item Description Item Description 1 Memory IC 2 eMMC Storage IC 3 Intel Edison Compatible Connector 4 Expansion Connector 1 5 E...

Page 15: ...g o Cortex A9 NEON MPE Media Processing Engine Co processor Level 2 Cache Unified instruction and data up to 1 MByte General Interrupt Controller GIC with 128 interrupt support Global Timer Snoop Cont...

Page 16: ...PICO IMX6 REV A1 HARDWARE MANUAL VER 1 01 JAN 28 2016 Page 16 of 64 Figure 9 NXP i MX6 Processor Scalability Overview Solo Duallite Dual Quad...

Page 17: ...ne It helps in maximizing system performance by off loading the various cores in dynamic data routing It has the following features Powered by a 16 bit Instruction Set micro RISC engine Multi channel...

Page 18: ...ding H 264 BP CBP MPEG 4 SP H 263 P0 P3 MJPEG BP max 192x8192 up to full HD 1920x1088 30fps GPU2Dv2 Hardware acceleration of 2D graphics Bit BLT and Stretch BLT Based on the Vivante GC320 IP core GPUV...

Page 19: ...ration Differential Data Strobe DQS DQS On chip DLL align DQ DQS and DQS transition with CK transition DM masks write data in at the both rising and falling edges of the data strobe All addresses and...

Page 20: ...ata strobe 8n bit prefetch architecture Differential clock inputs CK CK 8 internal banks Nominal and dynamic on die termination ODT for data strobe and mask signals Programmable CAS READ latency CL Pr...

Page 21: ...ansitions as well as features such as advanced power management scheme iNAND Ultra uses advanced Multi Level Cell MLC NAND flash technology enhanced by embedded flash management software running as fi...

Page 22: ...fication Ver 4 4 4 41 4 5 Bus mode o High speed e MMC protocol o Provide variable clock frequencies of 0 200MHz o Ten wire bus clock 1 bit command 8 bit data bus and a hardware reset Supports three di...

Page 23: ...ngston e MMC products follow the JEDEC e MMC 4 5 standard It is an ideal universal storage solutions for many electronic devices including smartphones tablet PCs PDAs eBook readers digital cameras rec...

Page 24: ...ustomers who require embedded 802 11ac Wi Fi Bluetooth features The SIP module is based on Broadcom 4339 chipset which is a WiFi BT SOC The Radio architecture high integration MAC BB chip provide exce...

Page 25: ...F19 SD2_CMD SDIO_CMD I O MMC SDIO Command C21 SD2_CLK SDIO_CLK I O MMC SDIO Clock R2 GPIO_16 WL_HOST_WAKE O General purpose interface pin This pin is high impedance on power up and reset Subsequently...

Page 26: ...I PCM data input U6 KEY_ROW1 AUD5_RXD BT_PCM_OUT O PCM data output W5 KEY_COL0 AUD5_TXC BT_PCM_CLK I O PCM clock U7 KEY_COL1 AUD5_TXFS BT_PCB_SYNC I O PCM sync signal R6 GPIO_4 BT_WAKE I Bluetooth dev...

Page 27: ...I operating at 50 MHz o Double data rate 4 bit Reduced GMII RGMII operating at 125 MHz For additional details please refer to the 10 100 1000 Mbps Ethernet MAC ENET chapter of the i MX6 Reference Manu...

Page 28: ...ons Support for 4k x 2k and 3D video formats Support for up to 16 bit Deep Color modes For additional details please refer to the Multimedia chapter of the i MX6 Reference Manual Table 7 HDMI Signal D...

Page 29: ...gle input data interface case Up to 170 MHz pixel clock WUXGA 1920x1200 o For dual input data interface case Up to 85 MHz per interface WXGA 1366x768 60 frames per second 35 blanking For additional de...

Page 30: ...0 16 bit protocols Supports HDTV standards SMPTE274 1080i p and SMPTE296 720p Scan Order progressive or interlaced Synchronization Programmable horizontal and vertical synchronization output signals D...

Page 31: ...bit 11 X1_34 R21 DISP0_DAT10 DISP0_DAT10 3V3 O LCD Pixel Data bit 10 X1_36 T25 DISP0_DAT9 DISP0_DAT9 3V3 O LCD Pixel Data bit 9 X1_38 R22 DISP0_DAT8 DISP0_DAT8 3V3 O LCD Pixel Data bit 8 X1_40 R24 DI...

Page 32: ...iance Specification for D PHY Version 1 00 00 14 May 2009 Supports up to 2 D PHY Data Lanes Bidirectional Communication and Escape Mode Support through Data Lane 0 Programmable display resolutions fro...

Page 33: ...PAD NAME Signal V I O Description X2_31 F4 CSI_CLK0M CSI_CLK0M 2V5 I MIPI Camera Serial Interface clock pair negative signal X2_33 F3 CSI_CLK0P CSI_CLK0P 2V5 I MIPI Camera Serial Interface clock pair...

Page 34: ...bus of the shared peripheral bus The ASRC Asynchronous Sample Rate Converter converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock T...

Page 35: ...d Advanced built in diagnostics including on chip sampling scope for easy debug Visibility controllability of hard macro functionality thru programmable registers in the design Over rides on all ASIC...

Page 36: ...nal analog logic also needs to support eSATA Hardware assisted Native Command Queuing NCQ for up to 32 entries For additional details please refer to the Serial Advanced Technology Attachment Controll...

Page 37: ...15 USB Host Signal Description PIN CPU BALL CPU PAD NAME Signal V I O Description X2_46 F10 USB_H1_DN USB_HOST_DN 3V3 I O Universal Serial Bus differential pair negative signal X2_48 E10 USB_H1_DP USB...

Page 38: ...fication version 3 0 Supports 1 bit 4 bit SD and SDIO modes 1 bit 4 bit The MMC SD SDIO host controller can support a single MMC SD SDIO card or device For additional details please refer to the Ultra...

Page 39: ...a CAN Bus transceiver and optional galvanic isolation should be incorporated on your carrier board For additional details please refer to the Flexible Controller Area Network FLEXCAN chapter of the i...

Page 40: ...additional details please refer to the Universal Asynchronous Receiver Transmitter UART chapter of the i MX6 Reference Manual Table 19 UART Signal Description PIN CPU BALL CPU PAD NAME Signal V I O De...

Page 41: ...and phase of the Chip Select SS and SPI Clock SCLK are configurable Direct Memory Access DMA support For additional details please refer to the Enhanced Configurable SPI ECSPI chapter of the i MX6 Ref...

Page 42: ...r to slave For additional details please refer to the I2C Controller I2C chapter of the i MX6 Reference Manual Table 21 I2 C Bus Signal Description PIN CPU BALL CPU PAD NAME Signal V I O Description X...

Page 43: ...n E1_24 P4 CSI0_MCLK GPIO_P24 1V8 I O General Purpose Input Output E1_25 P1 CSI0_PIXCLK GPIO_P25 1V8 I O General Purpose Input Output E1_26 N2 CSI0_VSYNC GPIO_P26 1V8 I O General Purpose Input Output...

Page 44: ...ompare and rollover For additional details please refer to the Pulse Width Modulation PWM chapter of the i MX6 Reference Manual Table 23 PWM Signal Description PIN CPU BALL CPU PAD NAME Signal V I O D...

Page 45: ...I O Description X2_3 M24 EIM_DA12 EIM_DA12 1V8 I Boot Select pin X2_5 N23 EIM_DA14 EIM_DA14 1V8 I Boot Select pin X2_7 M23 EIM_DA13 EIM_DA13 1V8 I Boot Select pin X2_9 L23 EIM_DA5 EIM_DA5 1V8 I Boot S...

Page 46: ...wer Signals Power Rail Nominal Input Input Range Maximum Input Ripple VSYS 4 pin 5V 4 2V 5 25V 50 mV 3 19 1 Power Management Signals The PICO IMX6 has the following set of signals to control the syste...

Page 47: ...arrier board For example the Maxim Integrated DS1337 connected over the general purpose I2C can be used Start Sequence VCC_RTC must come up at the same time or before VCC comes up Stop Sequence VCC mu...

Page 48: ...VSYS P System input power 4 0 to 5 25V E1_5 GND P Ground E1_6 VSYS P System input power 4 0 to 5 25V E1_7 NC Not Connected E1_8 3V3 P System 3 3V Output E1_9 GND P Ground E1_10 3V3 P System 3 3V Outp...

Page 49: ...t data signal E1_28 P3 CSI0_DATA_EN GPIO_P28 1V8 I O General Purpose Input Output E1_29 NC Not Connected E1_30 N6 CSI0_DAT8 GPIO_P30 1V8 I O General Purpose Input Output E1_31 NC Not Connected E1_32 N...

Page 50: ...l Peripheral Interface clock signal E1_56 P2 CSI0_DAT5 AUD3_TXD 1V8 O Integrated Interchip Sound I2S channel transmit data line E1_57 J23 EIM_CS1 CSPI2_MOSI 1V8 O Serial Peripheral Interface master ou...

Page 51: ...GND P Ground X1_20 U24 DISP0_DAT17 DISP0_DAT17 3V3 O LCD Pixel Data bit 17 X1_21 U4 LVDS0_TX1_N LVDS0_TX1_N 2V5 O LVDS differential pair 1 negative signal X1_22 T21 DISP0_DAT16 DISP0_DAT16 3V3 O LCD...

Page 52: ...RGMII transmit data 1 X1_54 P24 DISP0_DAT0 DISP0_DAT0 3V3 O LCD Pixel Data bit 0 X1_55 E21 RGMII_TD2 RGMII_TXD2 1V5 O RGMII transmit data 2 X1_56 P25 DI0_PIN4 DISP0_BLT_EN 3V3 O LCD backlight enable d...

Page 53: ...15 T7 KEY_ROW3 I2C2_SDA 3V3 I O I2C bus data line X2_16 K6 HDMI_D0P HDMI1_D0P 3V3 O HDMI differential pair 0 positive signal X2_17 GND P Ground X2_18 K5 HDMI_D0M HDMI1_D0M 3V3 O HDMI differential pair...

Page 54: ...GND P Ground X2_45 E1 CSI_D2M CSI_D2M 2V5 I MIPI Camera Serial Interface data pair 2 negative signal X2_46 F10 USB_H1_DN USB_HOST_DN 3V3 I O Universal Serial Bus differential pair negative signal X2_...

Page 55: ...0P 2V5 O MIPI Display Serial Interface clock pair positive signal X2_64 A3 PCIE_TXM PCIEA_TXN 2V5 O PCI Express Transmit output differential pair negative signal X2_65 R5 GPIO_8 GPIO_8 3V3 I O General...

Page 56: ...SD cardslot PICO Dwarf Carrierboard 4 mounting screws 8 mounting nuts Partnumber Description PICODWARFIMX6U10R1GBSDBW PICO Compute Module NXP i MX6 Duallite 1GB RAM 802 11ac Bluetooth 4 0 SD cardslot...

Page 57: ...MANUAL VER 1 01 JAN 28 2016 Page 57 of 64 5 2 PICO Compatible Displays 5 2 1 LVDSEXPANDER Translation Board to Connect to LVDS Panels Partnumber Description LVDSEXPANDER Expansion Translation Board t...

Page 58: ...ace LCD display 1024 600 resolution 250 nits with 4 wire resistive touchsensor Adaptor interface board LVDS signal cable Touch panel link cable NOTE To connect to PICO DWARF or PICO HOBBIT you will al...

Page 59: ...LCD display 1024 600 resolution 500 nits with PCAP multitouch touchsensor Adaptor interface board LVDS signal cable USB Touch panel link cable NOTE To connect to PICO DWARF or PICO HOBBIT you will als...

Page 60: ...ARDWARE MANUAL VER 1 01 JAN 28 2016 Page 60 of 64 5 3 Accessories 5 3 1 EDMANTP150A138045D2450BK Pack Content Partnumber Description EDMANTP150A138045D2450BK 4 5 dB 2 4 5 GHz black color antenna u FL...

Page 61: ...PICO Compute Module NXP i MX6 Solo 512MB RAM SD cardslot 802 11ac Bluetooth 4 0 Standard Part numbers featuring NXP i MX6 Solo booting from eMMC Part Number Description PICOIMX6S10R512NI4G PICO Comput...

Page 62: ...on Processor S i MX6 Solo U i MX6 Duallite D i MX6 Dual Q i MX6 Quad Proccesor speed 08 800 Mhz 10 1 Ghz Default 12 1 2 Ghz Memory R512 512 MB DDR3 R1GB 1GB DDR3 R2GB 2GB DDR3 Storage SD MicroSD Cards...

Page 63: ...tents or other intellectual property of the third party or a license from TechNexion under the patents or other intellectual property of TechNexion TechNexion products are not authorized for use in sa...

Page 64: ...this publication To the extent permitted by law no liability including liability to any person by reason of negligence will be accepted by TechNexion Ltd its subsidiaries or employees for any direct...

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