PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page
28
of
64
3.2. HDMI (High Definition Multi-Media Interface)
The HDMI interface available with PICO-IMX6
is based on the “HDMI transmitter” & “HDMI 3D Tx PHY”
integrated into the i.MX6 processor
. The “HDMI transmitter” combines video/display data from the IPU,
Audio data from i.MX6 memory & control/status data from the ARM complex, into TMDS data & clock
channels. The “HDMI 3D TX PHY” transmits the combined data by means of 3 TMDS data pairs and a
TMDS clock pair together with the DDC/I
2
C configuration signals.
The HDMI 3D TX PHY integrated into the i.MX6 processor supports the following standards & features:
High-Definition Multimedia Interface Specification, Version 1.4a
Digital Visual Interface, Revision 1.0
HDMI Compliance Test Specification, Version 1.4a
Support for up to 720p at 100Hz and 720i at 200Hz or 1080p at 60Hz and 1080i/720i at 120Hz
HDTV display resolutions and up to QXGA graphic display resolutions.
Support for 4k x 2k and 3D video formats
Support for up to 16-bit Deep Color modes
For additional details, please refer to the “Multimedia” chapter of the “i.MX6 Reference Manual”.
Table 7 - HDMI Signal Description
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O Description
X2_16
K6
HDMI_D0P
HDMI1_D0P
3V3
O
HDMI differential pair 0
positive signal
X2_18
K5
HDMI_D0M
HDMI1_D0M
3V3
O
HDMI differential pair 0
negative signal
X2_22
J4
HDMI_D1P
HDMI1_D1P
3V3
O
HDMI differential pair 1
positive signal
X2_24
J3
HDMI_D1M
HDMI1_D1M
3V3
O
HDMI differential pair 1
negative signal
X2_28
K4
HDMI_D2P
HDMI1_D2P
3V3
O
HDMI differential pair 2
positive signal
X2_30
K3
HDMI_D2M
HDMI1_D2M
3V3
O
HDMI differential pair 2
negative signal
X2_34
J6
HDMI_CLKP
HDMI1_CLKP
3V3
O
HDMI differential pair clock
positive signal
X2_36
J5
HDMI_CLKM
HDMI1_CLKM
3V3
O
HDMI differential pair clock
negative signal
X2_40
H19
EIM_A25
HDMI1_CEC
1V8
I/O
HDMI Consumer Electronics
Control
X2_42
K1
HDMI_HPD
HDMI1_HPD
3V3
I
HDMI/DP Hot plug detection
signal that serves as an
interrupt request
X2_13
U5
KEY_COL3
I2C2_SCL
3V3
I/O I
2
C bus clock line
X2_15
T7
KEY_ROW3
I2C2_SDA
3V3
I/O I
2
C bus data line
