TechNexion PICO-IMX6, Hardware Manual

Page: 29 / 64

PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page 29 of 64
3.3. LVDS Interface
The PICO-IMX6 is equipped with single LVDS Display interfaces. The LVDS Display Bridge (LDB)
connects the IPU (Image Processing Unit) to an External LVDS Display Interface. The purpose of the
LDB is to support flow of synchronous RGB data from the IPU to external display devices through LVDS
interface.
The LDB output complies with the EIA-644-A standard and supports the following features:

Connectivity to relevant devices - Displays with LVDS receivers.

Arranging the data as required by the external display receiver and by LVDS display standards.

Synchronization and control capabilities.

Data input interface (inside the i.MX6 processor)
o
RGB Data of 18 or 24 bits
o
Pixel clock
o
Control signals: HSYNC, VSYNC, DE, and 1 additional optional general purpose control
(I
2
C)

Single channel output data output interface
o
Total of up to 28 bits per data interface are transferred per pixel clock cycle.

Data Rates
o
Overall: LDB supports rates needed by WUXGA 16:10 aspect ratio (1920 x 1200 @ 60
frames per second, data rate supported up to 170 MHz)
o
For single input data interface case: Up to 170 MHz pixel clock (WUXGA 1920x1200)
o
For dual input data interface case: Up to 85 MHz per interface. (WXGA 1366x768 @ 60
frames per second, 35% blanking).
For additional details, p
lease refer to the “LVDS Display Bridge (LDB)” chapter of the “i.MX6 Reference
Manual”.
Table 8 - LVDS Signal Description
PIN
CPU
BALL
CPU PAD NAME Signal V I/O Description
X1_3 W2 LVDS0_TX3_N LVDS0_TX3_N 2V5 O
LVDS differential pair 3
negative signal
X1_4 D18 SD4_DAT0 LVDS0_BLT_EN 3V3 O LVDS panel backlight enable
X1_5 W1 LVDS0_TX3_P LVDS0_TX3_P 2V5 O
LVDS differential pair 3
positive signal
X1_6 B19 SD4_DAT1 LVDS0_BLT_CTRL 3V3 O LVDS panel backlight control
X1_9 V4 LVDS0_CLK_N LVDS0_CLK_N 2V5 O LVDS clock negative signal
X1_11 V3 LVDS0_CLK_P LVDS0_CLK_P 2V5 O LVDS clock positive signal
X1_15 V2 LVDS0_TX2_N LVDS0_TX2_N 2V5 O
LVDS differential pair 2
negative signal
X1_17 V1 LVDS0_TX2_P LVDS0_TX2_P 2V5 O
LVDS differential pair 2
positive signal
X1_21 U4 LVDS0_TX1_N LVDS0_TX1_N 2V5 O
LVDS differential pair 1
negative signal
X1_23 U3 LVDS0_TX1_P LVDS0_TX1_P 2V5 O
LVDS differential pair 1
positive signal
X1_27 U2 LVDS0_TX0_N LVDS0_TX0_N 2V5 O
LVDS differential pair 0
negative signal
X1_29 U1 LVDS0_TX0_P LVDS0_TX0_P 2V5 O
LVDS differential pair 0
positive signal
NOTE: LVDS_BLT_CTRL is also used as PWM3_1V8 signal.