PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
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15
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64
2. Core Components
2.1. NXP i.MX6 Cortex-A9 Multi-core Processor
The NXP i.MX6 processor is an implementation of the Single/Dual/Q
uad ARM Cortex™-A9 core, which
operates at frequencies up to 1.2 GHz. The i.MX6 provides a variety of interfaces and supports the
following main features:
Single / Dual / Quad Core ARM Cortex
™
-A9. Core configuration is symmetric, where each core
includes:
o
32 KByte L1 Instruction Cache
o
32 KByte L1 Data Cache
o
Private Timer and Watchdog
o
Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
Level 2 Cache
—
Unified instruction and data (up to 1 MByte)
General Interrupt Controller (GIC) with 128 interrupt support
Global Timer
Snoop Control Unit (SCU)
NEON MPE coprocessor:
o
SIMD Media Processing Architecture
o
NEON register file with 32x64-bit general-purpose registers
o
NEON Integer execute pipeline (ALU, Shift, MAC)
o
NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
o
NEON load/store and permute pipeline
Integrated Power Management unit:
o
Temperature Sensor for monitoring the die temperature
o
DVFS techniques for low power modes
o
Flexible clock gating control scheme
Multimedia Hardware Accelerators
Figure 8 - NXP i.MX6 Processor Blocks
