PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page
41
of
64
3.14. Serial Peripheral Interface (SPI)
The PICO -IMX6 features two Enhanced Configurable SPI ports, which are derived from the i.MX6
processor, integrated ECSPI IPs.
The following main features are supported:
Full-duplex synchronous serial interface
Master/Slave configurable
Transfer continuation function allows unlimited length data transfers
32-bit wide by 64-entry FIFO for both transmit and receive data
32-bit wide by 16-entry FIFO for HT message data
Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable Direct Memory
Access (DMA) support
For additional details, please refer to the “Enhanced Configurable SPI (ECSPI)” chapter of the “i.MX6
Reference Man
ual”.
Table 20 - SPI Channel Signal Description
PIN
CPU
BALL
CPU PAD NAME
Signal
V
I/O Description
E1_51
K22
EIM_LBA
SPI CS0
1V8
Serial Peripheral Interface
Chip Select 0 signal
E1_53
K20
EIM_RW
SPI CS1
1V8
Serial Peripheral Interface
Chip Select 1 signal
E1_55
H24
EIM_CS0
CSPI2_SCLK
1V8
O
Serial Peripheral Interface
clock signal
E1_57
J23
EIM_CS1
CSPI2_MOSI
1V8
O
Serial Peripheral Interface
master output slave input
signal
E1_59
J24
EIM_OE
CSPI2_MISO
1V8
I
Serial Peripheral Interface
master input slave output
signal
