Sun Microsystems Ultra 5, Service Manual

Page: 69 / 258

Chapter 3 Power-On Self-Test 3-21
Icache RAM Test
Sabre MCU Control & Status Regs Init and Tests
Init Sabre MCU Control & Status Regs
Initializing SC registers in SabreIO
Memory Probe and Init
Probe Memory
INFO: All the memory banks in 10 bit column mode
INFO: 32MB Bank 0
frequency = 301, refvalue = 73, no_of_banks = 2
INFO: MC0 = 0x00000000.80000549, MC1 = 0x00000000.0c4aab14
Malloc Post Memory
Memory Addr w/ Ecache
Load Post In Memory
Run POST from MEM
.........
loaded POST in memory
Map PROM/STACK/NVRAM in DMMU
Update Master Stack/Frame Pointers
All FPU Basic Tests
FPU Regs Test
FPU Move Regs Test
UPA Data Bus Line Test
Memory Tests
Init Memory
INFO: 32MB at bank 0 stack 0 (2 dimms per bank)
........................
INFO: 0MB at bank 0 stack 1
ERROR: DIMM Undetected on some sockets on the board!
ERROR: DIMM Undetected on some sockets on the board!
ECC Memory Addr Test
INFO: 32MB at bank 0 stack 0 (2 dimms per bank)
INFO: 0MB at bank 0 stack 1
ERROR: DIMM Undetected on some sockets on the board!
ERROR: DIMM Undetected on some sockets on the board!
CODE EXAMPLE 3-3
Typical Error Code Failure Message (Continued)
@(#) Sun Ultra 5/10 UPA/PCI 3.9 P2.1 Version 9 created 1997/08/
05 16:24