Sun Microsystems Ultra 5, Service Manual

Page: 219 / 258

Appendix C Functional Description C-19
C.1.5 ASICs
System ASICs include APB, PCIO, and RISC.
C.1.5.1 APB
The advanced PCI bridge (APB) ASIC provides a connection path between the
primary PCI bus and the two secondary PCI buses. APB features include:
■
32-bit memory addressing for PIO, 64-bit memory addressing (DACs) for DMA
■
16-bit I/O addressing
■
Full concurrences for primary and secondary PCI interfaces
■
72-byte FIFO data buffering on each of the DMA and PIO paths
■
Arbitration/prioritization
■
PIO reads and writes are in non-cacheable memory space
B50 Key B73 INTD3_L
B51 Key B74 Gnd
B75 INTD4_L B85 Gnd
B76 CLK2 B86 Gnd
B77 INTB2_L B87 +5V
B78 Gnd B88 +5V
B79 +5V B89 +5V
B80 CLK3 B90 +5V
B81 INTB3_L B91 Gnd
B82 Gnd B92 Reserved
B83 INTB4_L B93 Reserved
B84 CLK4 B94 Gnd
TABLE C-6
PCI Riser Board Pin Assignment (Continued)
Pin Number Signal Pin Number Signal