Sun Microsystems Ultra 5, Service Manual

Page: 229 / 258

Appendix C Functional Description C-29
C.3 Address Mapping
This section provides the overview of address partitioning and software-visible
registers and their respective functionality. The physical address associated with
each of these registers is listed, along with a brief description of the register. For
further details on the description of the registers and chips functionality refer to the
respective chip specification.
■
Section C.3.1 “Port Allocations” on page C-29
■
Section C.3.2 “PCI Address Assignments” on page C-30
C.3.1 Port Allocations
The following table lists the system port allocations. The CPU module divides the
physical address space among:
■
Main memory (DRAM)
■
PCI (which is further subdivided into the primary PCI bus (PCI-A) and the
secondary PCI bus (PCI-B bus) when the APB ASIC is used).
TABLE C-12
Port Allocations
Address Range in
PA<40:0>
Size Port Access Access Type
0x000.0000.0000 -
0x000.3FFF.FFFF 1 Gbyte Main memory Cacheable
0x000.4000.0000 -
0x1FF.FFFF.FFFF Do not use Undefined Cacheable
0x1FC.0000.0000 -
0x1FD.FFFF.FFFF 8 Gbytes UPA graphics Non-cacheable
0x1FE.0000.0000 -
0x1FF.FFFF.FFFF 8 Gbytes CPU IO Non-cacheable