Sun Microsystems Ultra 5, Service Manual

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Appendix C Functional Description C-31
Boot PROM
The PCIO ASIC is strapped so that the red mode trap address is:
■
UPA: 0x1FF.F000.0000
■
PCI: 0xF000.0000
■
EBus2: 0x00.0000
The following table lists the boot and flash PROM address assignments.
C.4 Interrupts
All interrupts are delivered to the CPU module through a packet-write scheme that
provides 24 bytes of data to the CPU module. Level sensitive software-acknowledge
interrupts, which would typically be communicated through dedicated interrupt
lines, are converted into interrupt packets and delivered to the CPU module.
The output of
INT_NUM
is registered externally and synchronized to the PCI clock
before being transferred to the CPU module. The following figure shows the
interrupt scheme block diagram and the following table summarizes the interrupt
routing.
TABLE C-14
Boot PROM/Flash PROM Address Assignments
Offset Register Description Type Size
0x00.0000 - 0xFF.FFFF Flash Prom/EPROM R 1 or 4 bytes