Sun Microsystems Ultra 5, Service Manual

Page: 221 / 258

Appendix C Functional Description C-21
FIGURE C-10
System Reset Functional Block Diagram
C.1.6 EBus2 Devices
The devices described in the sections below interface to the EBus2 within PCIO
ASIC. The EBus2 is a slave interface that provides slave cycles on the EBus2. The
EBus2 slave interface provides eight chip selects. The slave cycle timing(s) on the
EBus2 is programmable. Timing control is provided for 7 address ranges that
correspond to the EB_CS1 through EB_CS7 address ranges. This section discusses
the following topics.
■
Section C.1.6.1 “SuperIO” on page C-22
■
Section C.1.6.2 “Serial Communications Controller” on page C-23
■
Section C.1.6.3 “Flash PROM” on page C-23
■
Section C.1.6.4 “NVRAM/TOD” on page C-24
■
Section C.1.6.5 “Audio” on page C-24
Power
supply
Scan
Push-
button
Power_GOOD
SCAN control
BUTTON_POR
BUTTON_XIR
RISC
CPU
X_RESET_L
P_RESET_L
SYS_RESET_L
APB
RST_L
PCI_RESET_A
Enet
GFX
PCI_RESET_B
EIDE
EBus2
devices
interface
module
ASIC
ASIC
PCI slots
PCI_RESET_B
PCI_RESET_B
PCI_RESET_B