Sun Microsystems Ultra 5, Service Manual

Page: 65 / 258

Chapter 3 Power-On Self-Test 3-17
Interrupt Map (short) Reg Test
Interrupt Set/Clr Reg Test
Sabre IOMMU Regs Test
Sabre IOMMU RAM Address Test
Sabre IOMMU CAM Address Test
PBMA PCI Config Space Regs Test
PBMA Control/Status Reg Test
PBMA Diag Reg Test
Sabre IO Regs Test
All Advanced CPU Tests
IU ASI Access Test
FPU ASI Access Test
All CPU Error Reporting Tests
CPU Data Access Trap Test
CPU Addr Align Trap Test
DMMU Access Priv Page Test
DMMU Write Protected Page Test
All Advanced Sabre IOMMU Tests
Init Sabre
Consist DMA Rd, IOMMU miss Ebus Test
All Basic Cheerio Tests
Cheerio Ebus PCI Config Space Test
Cheerio Ethernet PCI Config Space Test
Cheerio Init
All Sabre IOMMU Error Reporting Tests
Init Sabre
PIO Read, Master Abort Test
PIO Read, Target Abort Test
Status of this POST run:PASS
manfacturing mode=OFF
Time Stamp [hour:min:sec] 00:10:33 [month/date year] 08/22 1997
Power On Selftest Completed
Software Power ON0.0000.0000.0000 ffff.ffff.f00b.4100
0002.3333.0200.001b
@(#) Sun Ultra 5/10 UPA/PCI 3.9 P2.1 Version 9 created 1997/08/
05 16:24
Clearing E$ Tags Done
Clearing I/D TLBs Done
CODE EXAMPLE 3-2 diag-level
Variable Set to
min
(Continued)
@(#) Sun Ultra 5/10 UPA/PCI 3.9 P2.1 Version 9 created 1997/08/
05 16:24