Stanford Research Systems SR844, User Manual

Page: 190 / 246

6-24 Circuit Descriptions
SR844 RF Lock-In Amplifier
Front Panel Output
The front panel output data (both channels) is written by the DSP to the FPGA once
every data sample period. The FPGA converts the parallel data to serial and sends the
serial data to dual D-to-A converter U920 along with the appropriate control signals.
R928 and Z923 filter the Channel 2 (Y) output with a 4.7
µ
s time constant. The filtered
output is amplified by U915C so as to provide outputs spanning
±
10V. The outputs go
to the front panel via connectors J5 (X) and J6 (Y) on the motherboard.