Stanford Research Systems SR844, User Manual

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Circuit Descriptions 6-19
SR844 RF Lock-In Amplifier
zero. C308–310 provide some input filtering, since the output of U304 can be much
faster than U310 is able to handle.
The output of U310 goes into a dual comparator which generates error signals (
RISING
and
-FALLING
) whenever U310.6 goes outside the range
±
0.3V nominal. This
corresponds to a phase excursion of
±
10
°
nominal. Typically
RISING
goes high when
the VCO frequency is going up, and
-FALLING
goes low when the VCO frequency is
going down. In either case the unit is not phase-locked. P313 is used to adjust the
threshold to 0.6V total range. P310 is used to adjust the LF357 offset so that its output is
centered wrt the comparator thresholds when the unit is phase-locked. N316 converts
the comparator output voltages to TTL levels and C316–317 provide some necessary
filtering to reduce the unlock sensitivity at low frequencies. The
RISING
and
-FALLING
outputs go to the Range Select section on the motherboard 84MBD.
XPLLF: Phase-Locked Loop Filter
This circuit implements a Type II second order loop filter with differential inputs; there
are numerous analog multiplexers to select the correct signal path depending on the loop
comparison frequency and the internal or external reference mode.
There are four signal paths in the feedback arms of the filter and two paths in the input
arms. The paths are selected depending on the control bits LF1,0 as shown below
LF1 LF0
Comparison
Frequency Range
Upper
Input Arm
Upper
Feedback
Arm
Lower
Input Arm
Lower
Feedback
Arm
0 0
25kHz – 100kHz N342C,D C352 N342B,A C363
0 1
100kHz – 800kHz N342C,D E351 N342B,A E362
1 0
800kHz – 6.25MHz N340C,D E350 N340B,A E360
1 1
6.25MHz – 200MHz N340C,D E348 N340B,A E358
The comparison frequency is the frequency at which the phase comparator operates. In
external mode, the phase comparator U304 (above) operates at the external reference
frequency, and the
LF1,0
bits can be directly found from the table above. In internal
mode the phase comparator is inside the synthesizer chip and operates at a divided down
frequency which is always below 2 MHz. Consequently the
LF
bits may be any of [
00,
01, 10
] depending on the programming of the synthesizer registers. Note that it is
possible for three successive internal frequencies to have three different settings of the
LF
bits ! (The synthesizer chip is on the motherboard 84MBD.)
Resistor networks R370–R375 convert the TTL levels of
INTUP
and
INTDN
(from the
synthesizer) into ECL levels; this guarantees that the inputs of U344 are always
≤
–0.8V
in both external and internal modes, which in turn permits the use of polarized feedback
capacitors. The Zener diode pairs D340–347 protect the multiplexers U340A and U341A
from overload transients during range switching.
The loop filter output U344.6 is the VCO tuning voltage
VTUNE
; it goes to the VCO. In
addition, a copy equal to half the tuning voltage,
VTUN2
, is generated by U345 and is