Stanford Research Systems SR844, User Manual

Page: 188 / 246

6-22 Circuit Descriptions
SR844 RF Lock-In Amplifier
U624 and U625 form a multiplexer to select 2
×
F
R
. On any range only one of these
multiplexers is active, the other chip’s output is held ECL–low. The two outputs are
combined by OR gates U626, U627. The output of U626 clocks the flip-flops U620,
U622 mentioned above, while the output of U627 goes through some delay lines to
buffer U629 and thence to the Chop circuit on 84CMX. The low-frequency inputs to
U625 come from TTL multiplexer U644.
U649 and U644 also provide signals at F
R
and 2
×
F
R
respectively for the rear panel TTL
out circuit. The TTL output is active only for ranges 2–7, ie below 1.56 MHz. Above
this
RANGR0
is high, which gates U648 off. Otherwise the TTL output is active and
U648 generates complementary
Q,-Q
signals which are attenuated to
±
200mV by N648,
N649 and then sent to the 84RTO board where the output drivers are located.
DVCE: Fixed Outputs
Other circuit functions require synchronous signals that are held to a specific octave
regardless of the operating frequency. U611C drives a 6–12 MHz signal to the Chop
circuit on 84CMX for the purpose of synchronizing the Chop (I.F.) waveform.
Fixed taps from U643 are buffered by U647 and U648. The 24–49 kHz tap is required
both by the Chop circuit on 84CMX and by the noise circuit on 84IFN. The 49–98 kHz
tap is required both by the Chop circuit on 84CMX and by the FPGA on 84DSP. The
latter is used to generate all the clocks and control signals required for data sampling,
which occurs at 49–98 kHz.
84DSP: Digital Signal Processing Board
This board is mounted underneath the motherboard 84MBD. This board contains the
following sections (a) the DSP chip (b) the FPGA (c) the Auxiliary Input A-to-D
converter (d) the Auxiliary Output D-to-A converter (e) the Front Panel Output D-to-A
converter.
DSP Chip
U900 is the DSP chip. The DSP is connected to the host ‘186 processor (on the CPU
board 844C) by means of the data bus
D0–D7
and the DSP control lines
DSP0–DSP7
.
All of these signals come through the platform interface on the motherboard. The DSP
also does parallel I/O over its own data bus
56D0–56D15
using control lines
56D16-56D18
. These control lines are the read and write strobes and a low-order
address bit that is used to distinguish X and Y data. In addition the DSP receives the
SYNCD
input from the Chop section of 84CMX and
RANG4D
from the Range Select
section of the motherboard. The former is used to ensure that demodulation (that is,
conversion of the I.F. signal to DC) within the DSP is in phase with the Chop waveform
applied to the Local Oscillator signals on 84CMX. The latter distinguishes upper half
and lower half of each octave, and is required so that the DSP uses the correct
demodulation waveform. Pin PC8 (U900.33) is connected to the Timer input U900.39
enabling the DSP timer to make measurements of the Data Sampling period, and